---

Detail Report for Assertions

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnown_A	0	0	603812269	603300375	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	603812269	50	0	0
tb.dut.IntrWdogKnown_A	0	0	603812269	603300375	0	0
tb.dut.IntrWkupKnown_A	0	0	603812269	603300375	0	0
tb.dut.RstReqKnown_A	0	0	2377556	2332606	0	0
tb.dut.TlOAReadyKnown_A	0	0	603812269	603300375	0	0
tb.dut.TlODValidKnown_A	0	0	603812269	603300375	0	0
tb.dut.WkupReqKnown_A	0	0	2377556	2332606	0	0
tb.dut.aon_timer_csr_assert.TlulOOBAddrErr_A	0	0	611401133	5653821	0	0
tb.dut.aon_timer_csr_assert.wdog_bark_thold_rd_A	0	0	611401133	145333	0	0
tb.dut.aon_timer_csr_assert.wdog_bite_thold_rd_A	0	0	611401133	127526	0	0
tb.dut.aon_timer_csr_assert.wdog_ctrl_rd_A	0	0	611401133	128078	0	0
tb.dut.aon_timer_csr_assert.wdog_regwen_rd_A	0	0	611401133	145469	0	0
tb.dut.aon_timer_csr_assert.wkup_ctrl_rd_A	0	0	611401133	127997	0	0
tb.dut.aon_timer_csr_assert.wkup_thold_rd_A	0	0	611401133	146239	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	611401133	29264058	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	611401133	610841022	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	611401133	610841022	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	611401133	27446980	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	611401133	610841022	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	611401133	610841022	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	321	321	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	611401322	22827071	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	611401133	3219525	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	611401322	2075902	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	611401322	13539	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	611401133	3657919	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	611401322	29264087	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	611401322	27446998	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	611401322	29264087	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	611401322	27446998	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	611401322	27446998	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	611401322	27446998	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	611401133	1875500	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	611401133	1225765	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	321	321	0	0
tb.dut.u_intr_hw.IntrTKind_A	0	0	197	197	0	0
tb.dut.u_lc_sync_escalate_en.NumCopiesMustBeGreaterZero_A	0	0	197	197	0	0
tb.dut.u_lc_sync_escalate_en.OutputsKnown_A	0	0	2377556	2332606	0	0
tb.dut.u_lc_sync_escalate_en.gen_flops.OutputDelay_A	0	0	2377556	2330358	0	579
tb.dut.u_reg.en2addrHit	0	0	611401133	312420	0	0
tb.dut.u_reg.reAfterRv	0	0	611401133	312418	0	0
tb.dut.u_reg.rePulse	0	0	611401133	75960	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	321	321	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	321	321	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	321	321	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	321	321	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	321	321	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	321	321	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	321	321	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	321	321	0	0
tb.dut.u_reg.u_wdog_bark_thold_cdc.BusySrcReqChk_A	0	0	611401133	2446063	0	0
tb.dut.u_reg.u_wdog_bark_thold_cdc.DstReqKnown_A	0	0	2411160	2341642	0	0
tb.dut.u_reg.u_wdog_bark_thold_cdc.SrcAckBusyChk_A	0	0	611401133	2663	0	0
tb.dut.u_reg.u_wdog_bark_thold_cdc.SrcBusyKnown_A	0	0	611401133	610841022	0	0
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	611401133	2663	0	0
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	2411160	2663	0	0
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	2411160	2585	0	0
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	611401133	2698	0	0
tb.dut.u_reg.u_wdog_bite_thold_cdc.BusySrcReqChk_A	0	0	611401133	2436292	0	0
tb.dut.u_reg.u_wdog_bite_thold_cdc.DstReqKnown_A	0	0	2411160	2341642	0	0
tb.dut.u_reg.u_wdog_bite_thold_cdc.SrcAckBusyChk_A	0	0	611401133	2647	0	0
tb.dut.u_reg.u_wdog_bite_thold_cdc.SrcBusyKnown_A	0	0	611401133	610841022	0	0
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	611401133	2647	0	0
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	2411160	2647	0	0
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	2411160	2571	0	0
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	611401133	2683	0	0
tb.dut.u_reg.u_wdog_count_cdc.BusySrcReqChk_A	0	0	611401133	5241717	0	0
tb.dut.u_reg.u_wdog_count_cdc.DstReqKnown_A	0	0	2411160	2341642	0	0
tb.dut.u_reg.u_wdog_count_cdc.SrcAckBusyChk_A	0	0	611401133	5116	0	0
tb.dut.u_reg.u_wdog_count_cdc.SrcBusyKnown_A	0	0	611401133	610841022	0	0
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	2411160	381	0	322
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	2411160	437	0	0
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	611401133	5557	0	0
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	2411160	3260	0	0
tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	2411160	5050	0	0
tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	611401133	5170	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.BusySrcReqChk_A	0	0	611401133	4536390	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.DstReqKnown_A	0	0	2411160	2341642	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.SrcAckBusyChk_A	0	0	611401133	4627	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.SrcBusyKnown_A	0	0	611401133	610841022	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	611401133	4627	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	2411160	4627	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	2411160	4551	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	611401133	4659	0	0
tb.dut.u_reg.u_wkup_cause_cdc.BusySrcReqChk_A	0	0	611401133	2295238	0	0
tb.dut.u_reg.u_wkup_cause_cdc.DstReqKnown_A	0	0	2411160	2341642	0	0
tb.dut.u_reg.u_wkup_cause_cdc.SrcAckBusyChk_A	0	0	611401133	2266	0	0
tb.dut.u_reg.u_wkup_cause_cdc.SrcBusyKnown_A	0	0	611401133	610841022	0	0
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	2411160	1096	0	321
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	2411160	1181	0	0
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	611401133	3453	0	0
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	2411160	2029	0	0
tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	2411160	2188	0	0
tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	611401133	2293	0	0
tb.dut.u_reg.u_wkup_count_cdc.BusySrcReqChk_A	0	0	611401133	5564529	0	0
tb.dut.u_reg.u_wkup_count_cdc.DstReqKnown_A	0	0	2411160	2341642	0	0
tb.dut.u_reg.u_wkup_count_cdc.SrcAckBusyChk_A	0	0	611401133	5107	0	0
tb.dut.u_reg.u_wkup_count_cdc.SrcBusyKnown_A	0	0	611401133	610841022	0	0
tb.dut.u_reg.u_wkup_count_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	2411160	2167	0	321
tb.dut.u_reg.u_wkup_count_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	2411160	2295	0	0
tb.dut.u_reg.u_wkup_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	611401133	7406	0	0
tb.dut.u_reg.u_wkup_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	2411160	3567	0	0
tb.dut.u_reg.u_wkup_count_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	2411160	5046	0	0
tb.dut.u_reg.u_wkup_count_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	611401133	5171	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.BusySrcReqChk_A	0	0	611401133	5123498	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.DstReqKnown_A	0	0	2411160	2341642	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.SrcAckBusyChk_A	0	0	611401133	5286	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.SrcBusyKnown_A	0	0	611401133	610841022	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	611401133	5286	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	2411160	5286	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	2411160	5210	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	611401133	5319	0	0
tb.dut.u_reg.u_wkup_thold_cdc.BusySrcReqChk_A	0	0	611401133	2454515	0	0
tb.dut.u_reg.u_wkup_thold_cdc.DstReqKnown_A	0	0	2411160	2341642	0	0
tb.dut.u_reg.u_wkup_thold_cdc.SrcAckBusyChk_A	0	0	611401133	2682	0	0
tb.dut.u_reg.u_wkup_thold_cdc.SrcBusyKnown_A	0	0	611401133	610841022	0	0
tb.dut.u_reg.u_wkup_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	611401133	2682	0	0
tb.dut.u_reg.u_wkup_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	2411160	2682	0	0
tb.dut.u_reg.u_wkup_thold_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	2411160	2602	0	0
tb.dut.u_reg.u_wkup_thold_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	611401133	2717	0	0
tb.dut.u_reg.wePulse	0	0	611401133	236458	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_lc_sync_escalate_en.gen_flops.OutputDelay_A	0	0	2377556	2330358	0	579
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	2411160	381	0	322
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	2411160	1096	0	321
tb.dut.u_reg.u_wkup_count_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	2411160	2167	0	321

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	611401322	98263	98263	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	611401322	681	681	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	611401322	1725	1725	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	611401322	1089	1089	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	611401322	1675	1675	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	611401322	885	885	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	611401322	421	421	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	611401322	737	737	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	611401322	1496	1496	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	611401322	11410	11410	275

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	611401322	98263	98263	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	611401322	681	681	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	611401322	1725	1725	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	611401322	1089	1089	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	611401322	1675	1675	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	611401322	885	885	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	611401322	421	421	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	611401322	737	737	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	611401322	1496	1496	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	611401322	11410	11410	275