Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.56 99.82 95.32 100.00 99.35 100.00 96.90


Total test records in report: 321
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T57 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2560408949 Jan 07 12:46:24 PM PST 24 Jan 07 12:48:42 PM PST 24 546052590 ps
T100 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3239892320 Jan 07 12:47:03 PM PST 24 Jan 07 12:48:58 PM PST 24 8432524236 ps
T84 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2529711131 Jan 07 12:46:24 PM PST 24 Jan 07 12:48:30 PM PST 24 518033042 ps
T102 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1015350439 Jan 07 12:46:07 PM PST 24 Jan 07 12:47:36 PM PST 24 4545873650 ps
T265 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3029176272 Jan 07 12:45:56 PM PST 24 Jan 07 12:47:41 PM PST 24 311167218 ps
T266 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2182561402 Jan 07 12:46:11 PM PST 24 Jan 07 12:48:30 PM PST 24 332511941 ps
T267 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4014531389 Jan 07 12:46:28 PM PST 24 Jan 07 12:48:30 PM PST 24 678709445 ps
T268 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4218895525 Jan 07 12:46:04 PM PST 24 Jan 07 12:47:34 PM PST 24 899411547 ps
T269 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2335160243 Jan 07 12:46:22 PM PST 24 Jan 07 12:47:51 PM PST 24 443213425 ps
T270 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1618855721 Jan 07 12:46:38 PM PST 24 Jan 07 12:48:01 PM PST 24 4150585492 ps
T58 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1443050300 Jan 07 12:46:28 PM PST 24 Jan 07 12:48:25 PM PST 24 340664078 ps
T271 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3880601595 Jan 07 12:46:35 PM PST 24 Jan 07 12:47:52 PM PST 24 425658427 ps
T59 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1375084999 Jan 07 12:45:51 PM PST 24 Jan 07 12:47:26 PM PST 24 7252674195 ps
T66 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3305255375 Jan 07 12:46:48 PM PST 24 Jan 07 12:48:06 PM PST 24 501435944 ps
T272 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.586761938 Jan 07 12:46:26 PM PST 24 Jan 07 12:47:50 PM PST 24 509878281 ps
T273 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.394987768 Jan 07 12:46:51 PM PST 24 Jan 07 12:49:12 PM PST 24 481628695 ps
T274 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.304366717 Jan 07 12:46:12 PM PST 24 Jan 07 12:48:08 PM PST 24 421905518 ps
T103 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1228923452 Jan 07 12:46:31 PM PST 24 Jan 07 12:47:55 PM PST 24 8606743915 ps
T275 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2919361722 Jan 07 12:46:38 PM PST 24 Jan 07 12:48:45 PM PST 24 11766639035 ps
T276 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2638709450 Jan 07 12:46:24 PM PST 24 Jan 07 12:48:44 PM PST 24 4489851414 ps
T277 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3346282925 Jan 07 12:45:45 PM PST 24 Jan 07 12:47:14 PM PST 24 344114220 ps
T278 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2910491334 Jan 07 12:46:52 PM PST 24 Jan 07 12:48:18 PM PST 24 525514978 ps
T279 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1812162486 Jan 07 12:45:38 PM PST 24 Jan 07 12:47:29 PM PST 24 726127095 ps
T280 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.793059049 Jan 07 12:45:58 PM PST 24 Jan 07 12:47:34 PM PST 24 502055025 ps
T281 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1793080462 Jan 07 12:45:52 PM PST 24 Jan 07 12:47:42 PM PST 24 392781780 ps
T282 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.132239994 Jan 07 12:47:00 PM PST 24 Jan 07 12:48:26 PM PST 24 487504451 ps
T283 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3754364536 Jan 07 12:46:21 PM PST 24 Jan 07 12:47:52 PM PST 24 459093043 ps
T284 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1786943744 Jan 07 12:46:42 PM PST 24 Jan 07 12:47:55 PM PST 24 447200916 ps
T74 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.514327255 Jan 07 12:46:26 PM PST 24 Jan 07 12:47:51 PM PST 24 421507682 ps
T285 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.4248394294 Jan 07 12:46:24 PM PST 24 Jan 07 12:48:35 PM PST 24 1495151980 ps
T286 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2265461254 Jan 07 12:46:09 PM PST 24 Jan 07 12:47:38 PM PST 24 489359022 ps
T287 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.977328243 Jan 07 12:46:07 PM PST 24 Jan 07 12:47:41 PM PST 24 577077361 ps
T288 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2225795959 Jan 07 12:46:46 PM PST 24 Jan 07 12:48:03 PM PST 24 1171548868 ps
T289 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.637747574 Jan 07 12:46:26 PM PST 24 Jan 07 12:47:46 PM PST 24 303824460 ps
T290 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.95754743 Jan 07 12:46:54 PM PST 24 Jan 07 12:48:27 PM PST 24 312571160 ps
T75 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.499786171 Jan 07 12:46:25 PM PST 24 Jan 07 12:47:53 PM PST 24 439798712 ps
T291 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1339088337 Jan 07 12:46:21 PM PST 24 Jan 07 12:47:52 PM PST 24 442082933 ps
T292 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4262908872 Jan 07 12:46:41 PM PST 24 Jan 07 12:47:59 PM PST 24 561261101 ps
T293 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.897313706 Jan 07 12:46:26 PM PST 24 Jan 07 12:48:14 PM PST 24 1922447155 ps
T294 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2999505901 Jan 07 12:46:52 PM PST 24 Jan 07 12:48:01 PM PST 24 435641304 ps
T295 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1350625017 Jan 07 12:46:39 PM PST 24 Jan 07 12:48:10 PM PST 24 506688954 ps
T296 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2374921736 Jan 07 12:46:33 PM PST 24 Jan 07 12:47:58 PM PST 24 1239202679 ps
T297 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2540918998 Jan 07 12:46:29 PM PST 24 Jan 07 12:47:44 PM PST 24 434932101 ps
T298 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2900138553 Jan 07 12:46:17 PM PST 24 Jan 07 12:48:34 PM PST 24 371398709 ps
T299 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1751146989 Jan 07 12:46:30 PM PST 24 Jan 07 12:48:03 PM PST 24 378901650 ps
T300 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.693019920 Jan 07 12:46:29 PM PST 24 Jan 07 12:47:55 PM PST 24 535069945 ps
T301 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.4293829667 Jan 07 12:47:03 PM PST 24 Jan 07 12:48:55 PM PST 24 464614780 ps
T302 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2375714498 Jan 07 12:46:31 PM PST 24 Jan 07 12:47:58 PM PST 24 414513924 ps
T303 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3626947667 Jan 07 12:46:53 PM PST 24 Jan 07 12:48:25 PM PST 24 4285904168 ps
T304 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2749403186 Jan 07 12:46:28 PM PST 24 Jan 07 12:47:52 PM PST 24 860463406 ps
T305 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1151534188 Jan 07 12:46:03 PM PST 24 Jan 07 12:47:44 PM PST 24 1073506287 ps
T306 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4069233166 Jan 07 12:46:48 PM PST 24 Jan 07 12:48:57 PM PST 24 301669256 ps
T101 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3604187394 Jan 07 12:46:26 PM PST 24 Jan 07 12:47:49 PM PST 24 8757043535 ps
T307 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1680134706 Jan 07 12:46:51 PM PST 24 Jan 07 12:48:42 PM PST 24 529157130 ps
T308 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.894994848 Jan 07 12:46:31 PM PST 24 Jan 07 12:48:08 PM PST 24 696319074 ps
T67 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3994388621 Jan 07 12:45:52 PM PST 24 Jan 07 12:47:23 PM PST 24 2216837200 ps
T309 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1120538937 Jan 07 12:45:59 PM PST 24 Jan 07 12:47:36 PM PST 24 488906146 ps
T310 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2199026027 Jan 07 12:46:52 PM PST 24 Jan 07 12:48:13 PM PST 24 2220684639 ps
T311 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2771220299 Jan 07 12:45:59 PM PST 24 Jan 07 12:47:40 PM PST 24 469298626 ps
T312 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.690257594 Jan 07 12:46:55 PM PST 24 Jan 07 12:48:15 PM PST 24 4578239134 ps
T104 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2284394481 Jan 07 12:46:32 PM PST 24 Jan 07 12:47:50 PM PST 24 8452232073 ps
T313 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3300214089 Jan 07 12:46:22 PM PST 24 Jan 07 12:48:00 PM PST 24 1212812462 ps
T314 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2580837842 Jan 07 12:46:04 PM PST 24 Jan 07 12:49:24 PM PST 24 451603943 ps
T68 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2343799124 Jan 07 12:46:08 PM PST 24 Jan 07 12:48:29 PM PST 24 472547227 ps
T315 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3349671213 Jan 07 12:46:16 PM PST 24 Jan 07 12:47:53 PM PST 24 507842543 ps
T316 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2602950780 Jan 07 12:46:41 PM PST 24 Jan 07 12:49:54 PM PST 24 273168936 ps
T317 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3356241674 Jan 07 12:45:57 PM PST 24 Jan 07 12:48:00 PM PST 24 441298716 ps
T318 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3310397530 Jan 07 12:45:52 PM PST 24 Jan 07 12:47:52 PM PST 24 1314032287 ps
T319 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2197555229 Jan 07 12:46:29 PM PST 24 Jan 07 12:48:06 PM PST 24 1066585697 ps
T320 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2047054240 Jan 07 12:46:46 PM PST 24 Jan 07 12:47:58 PM PST 24 354970684 ps
T321 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2706235857 Jan 07 12:46:21 PM PST 24 Jan 07 12:48:37 PM PST 24 2668962735 ps

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2370177042
Short name T8
Test name
Test status
Simulation time 108898546351 ps
CPU time 578.19 seconds
Started Jan 07 12:44:59 PM PST 24
Finished Jan 07 12:56:57 PM PST 24
Peak memory 198408 kb
Host smart-f7bb7fce-8e0e-499c-bbea-d80a6f5f48f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370177042 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2370177042
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2231936494
Short name T14
Test name
Test status
Simulation time 285123841703 ps
CPU time 806.96 seconds
Started Jan 07 12:44:21 PM PST 24
Finished Jan 07 12:59:16 PM PST 24
Peak memory 201744 kb
Host smart-4c1d799d-b28c-45b2-8bf8-f8e2361e7e1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231936494 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2231936494
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3146672758
Short name T91
Test name
Test status
Simulation time 51377346933 ps
CPU time 317.76 seconds
Started Jan 07 12:44:49 PM PST 24
Finished Jan 07 12:51:45 PM PST 24
Peak memory 197568 kb
Host smart-0fe30977-7de0-4ba3-8ccf-a570d7deb1b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146672758 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3146672758
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1838147382
Short name T31
Test name
Test status
Simulation time 7990519476 ps
CPU time 7.5 seconds
Started Jan 07 12:45:55 PM PST 24
Finished Jan 07 12:47:35 PM PST 24
Peak memory 197676 kb
Host smart-6791a6da-5a7e-4c6b-ad57-06278e31eff5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838147382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1838147382
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1132310909
Short name T15
Test name
Test status
Simulation time 88872919941 ps
CPU time 603.86 seconds
Started Jan 07 12:44:11 PM PST 24
Finished Jan 07 12:55:51 PM PST 24
Peak memory 205928 kb
Host smart-4c9098aa-517b-47a4-9c85-8bbc7ce31563
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132310909 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1132310909
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.61821052
Short name T17
Test name
Test status
Simulation time 8344693947 ps
CPU time 4.01 seconds
Started Jan 07 12:44:26 PM PST 24
Finished Jan 07 12:46:42 PM PST 24
Peak memory 214820 kb
Host smart-1b477b0b-6bd2-4b65-931b-5a218e70cedc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61821052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.61821052
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1767809289
Short name T41
Test name
Test status
Simulation time 85155571382 ps
CPU time 638.09 seconds
Started Jan 07 12:45:16 PM PST 24
Finished Jan 07 12:57:20 PM PST 24
Peak memory 199096 kb
Host smart-bc2b4711-22f6-4f03-bf8c-bc7434080573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767809289 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1767809289
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.628837365
Short name T110
Test name
Test status
Simulation time 29044899652 ps
CPU time 37.99 seconds
Started Jan 07 12:43:51 PM PST 24
Finished Jan 07 12:45:29 PM PST 24
Peak memory 193032 kb
Host smart-3a6c6420-6e0b-4e76-8946-c97a012aa2be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628837365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.628837365
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1919479987
Short name T116
Test name
Test status
Simulation time 108803079282 ps
CPU time 174.72 seconds
Started Jan 07 12:43:46 PM PST 24
Finished Jan 07 12:47:47 PM PST 24
Peak memory 182736 kb
Host smart-dc715e7f-87e3-4db6-b20a-8e7aba5bc71c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919479987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1919479987
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1068183640
Short name T90
Test name
Test status
Simulation time 155410791805 ps
CPU time 541.98 seconds
Started Jan 07 12:44:21 PM PST 24
Finished Jan 07 12:54:47 PM PST 24
Peak memory 197888 kb
Host smart-7b895e70-fd7e-4e5d-b1a7-67dfc367b416
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068183640 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1068183640
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2926034937
Short name T126
Test name
Test status
Simulation time 92558518576 ps
CPU time 62 seconds
Started Jan 07 12:44:33 PM PST 24
Finished Jan 07 12:46:54 PM PST 24
Peak memory 182768 kb
Host smart-cffb6a3c-69bb-4c93-b9c7-44846ddf9177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926034937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2926034937
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3304539875
Short name T107
Test name
Test status
Simulation time 61810373822 ps
CPU time 426.76 seconds
Started Jan 07 12:45:04 PM PST 24
Finished Jan 07 12:53:51 PM PST 24
Peak memory 197656 kb
Host smart-bd611b62-56b0-403c-a6e8-c15d7e00fb78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304539875 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3304539875
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3604187394
Short name T101
Test name
Test status
Simulation time 8757043535 ps
CPU time 3.08 seconds
Started Jan 07 12:46:26 PM PST 24
Finished Jan 07 12:47:49 PM PST 24
Peak memory 197712 kb
Host smart-500f3c91-0bf4-4762-acc5-c2ba6e41e5a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604187394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3604187394
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.497958321
Short name T7
Test name
Test status
Simulation time 1718270687 ps
CPU time 1.94 seconds
Started Jan 07 12:44:18 PM PST 24
Finished Jan 07 12:46:22 PM PST 24
Peak memory 182708 kb
Host smart-a5bf5ad3-3f90-4343-8879-c7b0ada35694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497958321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.497958321
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3169188420
Short name T53
Test name
Test status
Simulation time 539818910 ps
CPU time 1.98 seconds
Started Jan 07 12:46:17 PM PST 24
Finished Jan 07 12:48:12 PM PST 24
Peak memory 192080 kb
Host smart-adb6fbd1-37f7-4806-8758-070f3220fa9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169188420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3169188420
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1015350439
Short name T102
Test name
Test status
Simulation time 4545873650 ps
CPU time 2.41 seconds
Started Jan 07 12:46:07 PM PST 24
Finished Jan 07 12:47:36 PM PST 24
Peak memory 195808 kb
Host smart-0abc1832-2b63-455d-ba45-bdd3ad974045
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015350439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1015350439
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.405873311
Short name T30
Test name
Test status
Simulation time 1464459932 ps
CPU time 2.98 seconds
Started Jan 07 12:46:30 PM PST 24
Finished Jan 07 12:48:02 PM PST 24
Peak memory 194272 kb
Host smart-3ad50f29-4b17-4af2-b686-a7351dc4a560
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405873311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.405873311
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1754108911
Short name T39
Test name
Test status
Simulation time 227251259930 ps
CPU time 300.2 seconds
Started Jan 07 12:44:47 PM PST 24
Finished Jan 07 12:51:17 PM PST 24
Peak memory 205780 kb
Host smart-39336936-b777-4c6f-af8b-b7539212dd53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754108911 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1754108911
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2850759670
Short name T93
Test name
Test status
Simulation time 159420185787 ps
CPU time 581.32 seconds
Started Jan 07 12:44:58 PM PST 24
Finished Jan 07 12:56:08 PM PST 24
Peak memory 198692 kb
Host smart-79da9d40-2043-4b31-86f4-bfb5c6b0fe93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850759670 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2850759670
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2375714498
Short name T302
Test name
Test status
Simulation time 414513924 ps
CPU time 0.69 seconds
Started Jan 07 12:46:31 PM PST 24
Finished Jan 07 12:47:58 PM PST 24
Peak memory 183864 kb
Host smart-9108ce78-b18b-47e0-b309-08e9d1cf9103
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375714498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2375714498
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2919361722
Short name T275
Test name
Test status
Simulation time 11766639035 ps
CPU time 16.77 seconds
Started Jan 07 12:46:38 PM PST 24
Finished Jan 07 12:48:45 PM PST 24
Peak memory 193940 kb
Host smart-906c788f-1f6e-4c0f-ac0a-6c1a25a222d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919361722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2919361722
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.840443746
Short name T54
Test name
Test status
Simulation time 1060313712 ps
CPU time 0.74 seconds
Started Jan 07 12:45:53 PM PST 24
Finished Jan 07 12:47:27 PM PST 24
Peak memory 183668 kb
Host smart-526799f6-b544-470c-a692-49992e7953f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840443746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.840443746
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3872556849
Short name T262
Test name
Test status
Simulation time 472258348 ps
CPU time 0.6 seconds
Started Jan 07 12:46:41 PM PST 24
Finished Jan 07 12:49:39 PM PST 24
Peak memory 183744 kb
Host smart-e15fac9e-8df7-436c-aab2-86ce1425d864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872556849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3872556849
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3349671213
Short name T315
Test name
Test status
Simulation time 507842543 ps
CPU time 1.19 seconds
Started Jan 07 12:46:16 PM PST 24
Finished Jan 07 12:47:53 PM PST 24
Peak memory 183728 kb
Host smart-af281d5c-3921-4ad4-b6b9-52a4ae2b48cf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349671213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3349671213
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3310397530
Short name T318
Test name
Test status
Simulation time 1314032287 ps
CPU time 2.33 seconds
Started Jan 07 12:45:52 PM PST 24
Finished Jan 07 12:47:52 PM PST 24
Peak memory 194256 kb
Host smart-b4faed78-61c7-4831-b32c-519c5702640c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310397530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3310397530
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2749403186
Short name T304
Test name
Test status
Simulation time 860463406 ps
CPU time 1.6 seconds
Started Jan 07 12:46:28 PM PST 24
Finished Jan 07 12:47:52 PM PST 24
Peak memory 198616 kb
Host smart-9b929a8c-b4ec-44e4-8fb1-b36bce2500ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749403186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2749403186
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.894994848
Short name T308
Test name
Test status
Simulation time 696319074 ps
CPU time 1.63 seconds
Started Jan 07 12:46:31 PM PST 24
Finished Jan 07 12:48:08 PM PST 24
Peak memory 193888 kb
Host smart-971b1b58-c966-41f3-aae7-c3efa6f0ebf0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894994848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.894994848
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3994388621
Short name T67
Test name
Test status
Simulation time 2216837200 ps
CPU time 4.36 seconds
Started Jan 07 12:45:52 PM PST 24
Finished Jan 07 12:47:23 PM PST 24
Peak memory 194920 kb
Host smart-76e902a0-48c7-4973-8a63-ce3bace8c2c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994388621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3994388621
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3300214089
Short name T313
Test name
Test status
Simulation time 1212812462 ps
CPU time 0.92 seconds
Started Jan 07 12:46:22 PM PST 24
Finished Jan 07 12:48:00 PM PST 24
Peak memory 183792 kb
Host smart-a11ad3c2-a6c4-47a4-9d66-23c9dbe80def
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300214089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3300214089
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3346282925
Short name T277
Test name
Test status
Simulation time 344114220 ps
CPU time 0.8 seconds
Started Jan 07 12:45:45 PM PST 24
Finished Jan 07 12:47:14 PM PST 24
Peak memory 183784 kb
Host smart-2f1457d0-7289-4042-bb41-aed50b3bd190
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346282925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3346282925
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.304366717
Short name T274
Test name
Test status
Simulation time 421905518 ps
CPU time 0.53 seconds
Started Jan 07 12:46:12 PM PST 24
Finished Jan 07 12:48:08 PM PST 24
Peak memory 183856 kb
Host smart-e8e2739e-f36e-48d7-a05d-9df85d027843
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304366717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.304366717
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1791613547
Short name T240
Test name
Test status
Simulation time 465286040 ps
CPU time 1.61 seconds
Started Jan 07 12:46:44 PM PST 24
Finished Jan 07 12:48:16 PM PST 24
Peak memory 198556 kb
Host smart-23e4e67e-c7ad-45a7-a896-a51352ebdbd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791613547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1791613547
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3902034359
Short name T252
Test name
Test status
Simulation time 419275910 ps
CPU time 0.64 seconds
Started Jan 07 12:46:06 PM PST 24
Finished Jan 07 12:47:30 PM PST 24
Peak memory 194808 kb
Host smart-d73494c5-71dd-40a2-ab6c-516fa33c0538
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902034359 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3902034359
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.499786171
Short name T75
Test name
Test status
Simulation time 439798712 ps
CPU time 0.65 seconds
Started Jan 07 12:46:25 PM PST 24
Finished Jan 07 12:47:53 PM PST 24
Peak memory 183776 kb
Host smart-b321946a-56da-4c62-aaaa-fc0ba92d3aee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499786171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.499786171
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.260034007
Short name T257
Test name
Test status
Simulation time 470741784 ps
CPU time 0.73 seconds
Started Jan 07 12:46:39 PM PST 24
Finished Jan 07 12:48:10 PM PST 24
Peak memory 183548 kb
Host smart-a780e79c-f3cf-4eff-a560-d65640cca31d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260034007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.260034007
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3533442995
Short name T254
Test name
Test status
Simulation time 331717100 ps
CPU time 1.59 seconds
Started Jan 07 12:46:05 PM PST 24
Finished Jan 07 12:47:37 PM PST 24
Peak memory 198540 kb
Host smart-4349717d-5aed-495b-b29e-13d90e2fbc7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533442995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3533442995
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3754364536
Short name T283
Test name
Test status
Simulation time 459093043 ps
CPU time 0.89 seconds
Started Jan 07 12:46:21 PM PST 24
Finished Jan 07 12:47:52 PM PST 24
Peak memory 194824 kb
Host smart-51a0d310-e4b2-4901-a96a-729b2c41d802
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754364536 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3754364536
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3471791381
Short name T29
Test name
Test status
Simulation time 348463829 ps
CPU time 0.69 seconds
Started Jan 07 12:46:21 PM PST 24
Finished Jan 07 12:47:54 PM PST 24
Peak memory 193060 kb
Host smart-0d8b2733-b5e8-4bd5-a1e4-bedb3483baa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471791381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3471791381
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3208678301
Short name T79
Test name
Test status
Simulation time 471817189 ps
CPU time 1.17 seconds
Started Jan 07 12:46:24 PM PST 24
Finished Jan 07 12:48:36 PM PST 24
Peak memory 183552 kb
Host smart-56fe74de-6807-444f-98a6-3ebee6fefd4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208678301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3208678301
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1151534188
Short name T305
Test name
Test status
Simulation time 1073506287 ps
CPU time 1.21 seconds
Started Jan 07 12:46:03 PM PST 24
Finished Jan 07 12:47:44 PM PST 24
Peak memory 194132 kb
Host smart-c0256a43-0461-4bf0-9b86-ee42a57644e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151534188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1151534188
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1613347463
Short name T264
Test name
Test status
Simulation time 1005458168 ps
CPU time 2.1 seconds
Started Jan 07 12:46:05 PM PST 24
Finished Jan 07 12:47:43 PM PST 24
Peak memory 198548 kb
Host smart-643f19ab-b6e8-442e-8ca4-f330b078f03d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613347463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1613347463
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1006358869
Short name T99
Test name
Test status
Simulation time 8815828730 ps
CPU time 7.91 seconds
Started Jan 07 12:46:22 PM PST 24
Finished Jan 07 12:48:20 PM PST 24
Peak memory 197636 kb
Host smart-c8eb4811-0648-4928-baa0-a5cf17091e79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006358869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1006358869
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4262908872
Short name T292
Test name
Test status
Simulation time 561261101 ps
CPU time 1.52 seconds
Started Jan 07 12:46:41 PM PST 24
Finished Jan 07 12:47:59 PM PST 24
Peak memory 195588 kb
Host smart-64b2192f-6bdb-4443-afa5-92a9b61669aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262908872 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.4262908872
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1443050300
Short name T58
Test name
Test status
Simulation time 340664078 ps
CPU time 0.7 seconds
Started Jan 07 12:46:28 PM PST 24
Finished Jan 07 12:48:25 PM PST 24
Peak memory 193152 kb
Host smart-8769f47f-295f-49dc-a5e5-89374de26f89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443050300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1443050300
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.897313706
Short name T293
Test name
Test status
Simulation time 1922447155 ps
CPU time 4.89 seconds
Started Jan 07 12:46:26 PM PST 24
Finished Jan 07 12:48:14 PM PST 24
Peak memory 195156 kb
Host smart-342b9224-b775-445b-9a40-d4c5ad9783c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897313706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.897313706
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.453252238
Short name T35
Test name
Test status
Simulation time 357597153 ps
CPU time 0.95 seconds
Started Jan 07 12:46:24 PM PST 24
Finished Jan 07 12:48:36 PM PST 24
Peak memory 194948 kb
Host smart-a4717073-1277-4185-bf92-747390969a2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453252238 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.453252238
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1606678233
Short name T55
Test name
Test status
Simulation time 515340231 ps
CPU time 0.74 seconds
Started Jan 07 12:46:29 PM PST 24
Finished Jan 07 12:48:03 PM PST 24
Peak memory 183860 kb
Host smart-1afb525e-ac3d-4a3c-aa39-3eb112a3fde1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606678233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1606678233
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2999505901
Short name T294
Test name
Test status
Simulation time 435641304 ps
CPU time 0.58 seconds
Started Jan 07 12:46:52 PM PST 24
Finished Jan 07 12:48:01 PM PST 24
Peak memory 183528 kb
Host smart-0a9851b4-85f3-47d6-9884-4ec354bad5ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999505901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2999505901
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2199026027
Short name T310
Test name
Test status
Simulation time 2220684639 ps
CPU time 1.51 seconds
Started Jan 07 12:46:52 PM PST 24
Finished Jan 07 12:48:13 PM PST 24
Peak memory 195320 kb
Host smart-d9eb964f-5fcf-4c78-9fa9-6f1602c2f04e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199026027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2199026027
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2142827543
Short name T65
Test name
Test status
Simulation time 489907263 ps
CPU time 1.73 seconds
Started Jan 07 12:46:09 PM PST 24
Finished Jan 07 12:47:47 PM PST 24
Peak memory 198180 kb
Host smart-e9ae3c27-c1b4-4092-a529-8f83298dad52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142827543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2142827543
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3626947667
Short name T303
Test name
Test status
Simulation time 4285904168 ps
CPU time 3.86 seconds
Started Jan 07 12:46:53 PM PST 24
Finished Jan 07 12:48:25 PM PST 24
Peak memory 197140 kb
Host smart-5ecaaec0-b968-4b49-85b1-6531d4f53f13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626947667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3626947667
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2580837842
Short name T314
Test name
Test status
Simulation time 451603943 ps
CPU time 0.8 seconds
Started Jan 07 12:46:04 PM PST 24
Finished Jan 07 12:49:24 PM PST 24
Peak memory 196860 kb
Host smart-af3d200a-e3e6-4e31-ab63-06d0e02541b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580837842 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2580837842
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2014589844
Short name T261
Test name
Test status
Simulation time 396346475 ps
CPU time 0.79 seconds
Started Jan 07 12:46:31 PM PST 24
Finished Jan 07 12:48:43 PM PST 24
Peak memory 183872 kb
Host smart-b430680d-1fe4-49cd-a00d-a83a26977712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014589844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2014589844
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2056138906
Short name T243
Test name
Test status
Simulation time 547684481 ps
CPU time 2.15 seconds
Started Jan 07 12:46:49 PM PST 24
Finished Jan 07 12:48:04 PM PST 24
Peak memory 198596 kb
Host smart-489c6aa0-8fd0-489f-9c76-3b83dc127a89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056138906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2056138906
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1680134706
Short name T307
Test name
Test status
Simulation time 529157130 ps
CPU time 1.34 seconds
Started Jan 07 12:46:51 PM PST 24
Finished Jan 07 12:48:42 PM PST 24
Peak memory 194856 kb
Host smart-4070e5b7-2d85-4674-bcc6-e0971a8f791b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680134706 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1680134706
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2265461254
Short name T286
Test name
Test status
Simulation time 489359022 ps
CPU time 0.71 seconds
Started Jan 07 12:46:09 PM PST 24
Finished Jan 07 12:47:38 PM PST 24
Peak memory 183572 kb
Host smart-0aa32ebe-0b92-4595-ba55-157ef6941335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265461254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2265461254
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2197555229
Short name T319
Test name
Test status
Simulation time 1066585697 ps
CPU time 2.15 seconds
Started Jan 07 12:46:29 PM PST 24
Finished Jan 07 12:48:06 PM PST 24
Peak memory 192760 kb
Host smart-0ff53371-4e9a-41b3-afe2-bc5df8d15d55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197555229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2197555229
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1751146989
Short name T299
Test name
Test status
Simulation time 378901650 ps
CPU time 1.96 seconds
Started Jan 07 12:46:30 PM PST 24
Finished Jan 07 12:48:03 PM PST 24
Peak memory 198628 kb
Host smart-10e5753c-3a52-44e3-9b1d-13269462c75e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751146989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1751146989
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2978258825
Short name T32
Test name
Test status
Simulation time 3888411508 ps
CPU time 3.54 seconds
Started Jan 07 12:46:55 PM PST 24
Finished Jan 07 12:48:22 PM PST 24
Peak memory 196092 kb
Host smart-95b50755-7327-4867-a554-0ce4ab700819
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978258825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2978258825
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2529711131
Short name T84
Test name
Test status
Simulation time 518033042 ps
CPU time 1.07 seconds
Started Jan 07 12:46:24 PM PST 24
Finished Jan 07 12:48:30 PM PST 24
Peak memory 183804 kb
Host smart-fbae7f22-ada2-40b3-ada6-455ed5935c8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529711131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2529711131
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2540918998
Short name T297
Test name
Test status
Simulation time 434932101 ps
CPU time 0.64 seconds
Started Jan 07 12:46:29 PM PST 24
Finished Jan 07 12:47:44 PM PST 24
Peak memory 183548 kb
Host smart-56cf0b6c-67e1-4824-96dd-f8e12ddbf5c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540918998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2540918998
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.4248394294
Short name T285
Test name
Test status
Simulation time 1495151980 ps
CPU time 2.63 seconds
Started Jan 07 12:46:24 PM PST 24
Finished Jan 07 12:48:35 PM PST 24
Peak memory 194148 kb
Host smart-34887b65-2a4b-44f7-86bf-38a56947862c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248394294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.4248394294
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4218895525
Short name T268
Test name
Test status
Simulation time 899411547 ps
CPU time 2.47 seconds
Started Jan 07 12:46:04 PM PST 24
Finished Jan 07 12:47:34 PM PST 24
Peak memory 198636 kb
Host smart-2241d22c-7bcd-4183-85c6-a1bc2feacb10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218895525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4218895525
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3687631213
Short name T61
Test name
Test status
Simulation time 497175134 ps
CPU time 1.26 seconds
Started Jan 07 12:47:05 PM PST 24
Finished Jan 07 12:48:19 PM PST 24
Peak memory 183724 kb
Host smart-539177a0-d343-4710-9bbb-8a099d0c2cf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687631213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3687631213
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2182561402
Short name T266
Test name
Test status
Simulation time 332511941 ps
CPU time 0.93 seconds
Started Jan 07 12:46:11 PM PST 24
Finished Jan 07 12:48:30 PM PST 24
Peak memory 183440 kb
Host smart-6014031a-7518-4862-a55f-032347574f87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182561402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2182561402
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4069233166
Short name T306
Test name
Test status
Simulation time 301669256 ps
CPU time 0.69 seconds
Started Jan 07 12:46:48 PM PST 24
Finished Jan 07 12:48:57 PM PST 24
Peak memory 194740 kb
Host smart-c44a0a53-6db1-498a-bb38-218c70cc0414
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069233166 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.4069233166
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3305255375
Short name T66
Test name
Test status
Simulation time 501435944 ps
CPU time 0.72 seconds
Started Jan 07 12:46:48 PM PST 24
Finished Jan 07 12:48:06 PM PST 24
Peak memory 183780 kb
Host smart-f66c1a9d-57ba-4dd9-b716-5c03a8d1afd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305255375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3305255375
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2706235857
Short name T321
Test name
Test status
Simulation time 2668962735 ps
CPU time 3.6 seconds
Started Jan 07 12:46:21 PM PST 24
Finished Jan 07 12:48:37 PM PST 24
Peak memory 195352 kb
Host smart-a0676f0e-f65a-4e83-9cf1-5a1fac6dffb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706235857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2706235857
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3239892320
Short name T100
Test name
Test status
Simulation time 8432524236 ps
CPU time 2.56 seconds
Started Jan 07 12:47:03 PM PST 24
Finished Jan 07 12:48:58 PM PST 24
Peak memory 197716 kb
Host smart-afb7d7d0-a8db-4415-a529-54b3c231ec96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239892320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3239892320
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.586761938
Short name T272
Test name
Test status
Simulation time 509878281 ps
CPU time 0.74 seconds
Started Jan 07 12:46:26 PM PST 24
Finished Jan 07 12:47:50 PM PST 24
Peak memory 194736 kb
Host smart-8f3ffb63-7920-4b22-a032-ee4615c80f8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586761938 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.586761938
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3061771778
Short name T81
Test name
Test status
Simulation time 457503715 ps
CPU time 0.71 seconds
Started Jan 07 12:46:40 PM PST 24
Finished Jan 07 12:48:12 PM PST 24
Peak memory 183800 kb
Host smart-43dee4c4-32ab-4e8d-bd66-7cd21e489134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061771778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3061771778
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2323811962
Short name T82
Test name
Test status
Simulation time 1680257540 ps
CPU time 3.25 seconds
Started Jan 07 12:46:14 PM PST 24
Finished Jan 07 12:48:46 PM PST 24
Peak memory 194904 kb
Host smart-c5b62b33-55b7-47e6-9340-a6d2de826d2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323811962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2323811962
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1618855721
Short name T270
Test name
Test status
Simulation time 4150585492 ps
CPU time 2.51 seconds
Started Jan 07 12:46:38 PM PST 24
Finished Jan 07 12:48:01 PM PST 24
Peak memory 197096 kb
Host smart-43f28ea7-2c3a-4b4c-8c29-08e4dd3f2ef3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618855721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1618855721
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2560408949
Short name T57
Test name
Test status
Simulation time 546052590 ps
CPU time 0.81 seconds
Started Jan 07 12:46:24 PM PST 24
Finished Jan 07 12:48:42 PM PST 24
Peak memory 183864 kb
Host smart-57895b23-d587-4712-aeb2-ee326da2d842
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560408949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2560408949
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4014531389
Short name T267
Test name
Test status
Simulation time 678709445 ps
CPU time 1.45 seconds
Started Jan 07 12:46:28 PM PST 24
Finished Jan 07 12:48:30 PM PST 24
Peak memory 183768 kb
Host smart-dab45753-54ab-4765-88b6-2977046bdae7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014531389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.4014531389
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2073702717
Short name T258
Test name
Test status
Simulation time 318686077 ps
CPU time 0.75 seconds
Started Jan 07 12:46:46 PM PST 24
Finished Jan 07 12:48:10 PM PST 24
Peak memory 183800 kb
Host smart-3d6a6c19-3fe0-4652-8106-eb535cec7a90
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073702717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2073702717
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.838622250
Short name T83
Test name
Test status
Simulation time 729216865 ps
CPU time 1 seconds
Started Jan 07 12:45:53 PM PST 24
Finished Jan 07 12:47:32 PM PST 24
Peak memory 193344 kb
Host smart-11258eb2-51d1-45b3-9af2-7b7471fe48e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838622250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.838622250
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.977328243
Short name T287
Test name
Test status
Simulation time 577077361 ps
CPU time 2.21 seconds
Started Jan 07 12:46:07 PM PST 24
Finished Jan 07 12:47:41 PM PST 24
Peak memory 198488 kb
Host smart-25b380e0-d783-462f-a6f1-9d2f40372849
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977328243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.977328243
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.690257594
Short name T312
Test name
Test status
Simulation time 4578239134 ps
CPU time 1.36 seconds
Started Jan 07 12:46:55 PM PST 24
Finished Jan 07 12:48:15 PM PST 24
Peak memory 196132 kb
Host smart-fdb98804-908f-4c09-8b14-1797feb315ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690257594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.690257594
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1925058084
Short name T62
Test name
Test status
Simulation time 479907815 ps
CPU time 0.73 seconds
Started Jan 07 12:46:44 PM PST 24
Finished Jan 07 12:48:36 PM PST 24
Peak memory 183584 kb
Host smart-629f9893-3e4d-4619-9c81-ebbbc189aa88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925058084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1925058084
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3421132197
Short name T77
Test name
Test status
Simulation time 378079476 ps
CPU time 0.53 seconds
Started Jan 07 12:46:21 PM PST 24
Finished Jan 07 12:48:33 PM PST 24
Peak memory 183492 kb
Host smart-3816136e-3b3f-4f82-a4b5-42e49645010e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421132197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3421132197
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1579880106
Short name T247
Test name
Test status
Simulation time 350824306 ps
CPU time 0.64 seconds
Started Jan 07 12:46:51 PM PST 24
Finished Jan 07 12:48:30 PM PST 24
Peak memory 183844 kb
Host smart-6b752aff-4682-480d-beec-367c78da8a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579880106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1579880106
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3002443879
Short name T245
Test name
Test status
Simulation time 322570707 ps
CPU time 1.03 seconds
Started Jan 07 12:46:50 PM PST 24
Finished Jan 07 12:48:20 PM PST 24
Peak memory 183520 kb
Host smart-484b5240-1118-45b6-b75f-dec842333f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002443879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3002443879
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1252868585
Short name T244
Test name
Test status
Simulation time 347341236 ps
CPU time 0.78 seconds
Started Jan 07 12:46:37 PM PST 24
Finished Jan 07 12:48:58 PM PST 24
Peak memory 183564 kb
Host smart-c3f0116f-84f8-419c-9a8f-3e55c768cdb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252868585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1252868585
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1818588654
Short name T251
Test name
Test status
Simulation time 525970430 ps
CPU time 0.82 seconds
Started Jan 07 12:46:46 PM PST 24
Finished Jan 07 12:48:10 PM PST 24
Peak memory 183724 kb
Host smart-c0cb2074-8b3c-49dd-a3b9-76fccba35da8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818588654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1818588654
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1238116338
Short name T246
Test name
Test status
Simulation time 371938125 ps
CPU time 0.71 seconds
Started Jan 07 12:46:50 PM PST 24
Finished Jan 07 12:48:41 PM PST 24
Peak memory 183512 kb
Host smart-a1f7e25a-8778-461c-87e9-abd092e08d82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238116338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1238116338
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1736682883
Short name T260
Test name
Test status
Simulation time 443370391 ps
CPU time 0.58 seconds
Started Jan 07 12:46:57 PM PST 24
Finished Jan 07 12:48:17 PM PST 24
Peak memory 183548 kb
Host smart-860505d2-4772-46f6-beda-c0a6d3692a25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736682883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1736682883
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3569187359
Short name T242
Test name
Test status
Simulation time 430906660 ps
CPU time 0.84 seconds
Started Jan 07 12:46:48 PM PST 24
Finished Jan 07 12:48:31 PM PST 24
Peak memory 183564 kb
Host smart-f3370ee2-d871-45f3-bc8c-64cc1fc61576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569187359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3569187359
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.394987768
Short name T273
Test name
Test status
Simulation time 481628695 ps
CPU time 0.92 seconds
Started Jan 07 12:46:51 PM PST 24
Finished Jan 07 12:49:12 PM PST 24
Peak memory 183624 kb
Host smart-9c2bdec0-5484-42be-9040-fe5a1fd99638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394987768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.394987768
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4093241938
Short name T76
Test name
Test status
Simulation time 465263895 ps
CPU time 1 seconds
Started Jan 07 12:46:46 PM PST 24
Finished Jan 07 12:48:12 PM PST 24
Peak memory 183800 kb
Host smart-68935e4b-079c-4247-9044-514df45ce205
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093241938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.4093241938
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1812162486
Short name T279
Test name
Test status
Simulation time 726127095 ps
CPU time 1.66 seconds
Started Jan 07 12:45:38 PM PST 24
Finished Jan 07 12:47:29 PM PST 24
Peak memory 183728 kb
Host smart-095a3dde-ccda-4afb-9c9b-da0280e6b396
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812162486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1812162486
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2335160243
Short name T269
Test name
Test status
Simulation time 443213425 ps
CPU time 0.88 seconds
Started Jan 07 12:46:22 PM PST 24
Finished Jan 07 12:47:51 PM PST 24
Peak memory 197340 kb
Host smart-84c562d4-aaaa-481b-acf0-331d3be94ccf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335160243 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2335160243
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3029176272
Short name T265
Test name
Test status
Simulation time 311167218 ps
CPU time 0.95 seconds
Started Jan 07 12:45:56 PM PST 24
Finished Jan 07 12:47:41 PM PST 24
Peak memory 183808 kb
Host smart-03651264-3c16-41f3-ae4c-8c9d49115fe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029176272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3029176272
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1793080462
Short name T281
Test name
Test status
Simulation time 392781780 ps
CPU time 0.61 seconds
Started Jan 07 12:45:52 PM PST 24
Finished Jan 07 12:47:42 PM PST 24
Peak memory 183504 kb
Host smart-9ee6d0e1-0fc2-4887-9394-d1463888c201
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793080462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1793080462
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.832204201
Short name T80
Test name
Test status
Simulation time 980998528 ps
CPU time 1.93 seconds
Started Jan 07 12:46:45 PM PST 24
Finished Jan 07 12:48:09 PM PST 24
Peak memory 192772 kb
Host smart-1a844320-68b0-4985-b79c-9875ed76ffdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832204201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.832204201
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3679482674
Short name T33
Test name
Test status
Simulation time 4748381522 ps
CPU time 7.95 seconds
Started Jan 07 12:46:09 PM PST 24
Finished Jan 07 12:47:49 PM PST 24
Peak memory 195808 kb
Host smart-0ad670bd-44b9-4ae1-8357-3ebfc64ab7d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679482674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3679482674
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2602950780
Short name T316
Test name
Test status
Simulation time 273168936 ps
CPU time 0.96 seconds
Started Jan 07 12:46:41 PM PST 24
Finished Jan 07 12:49:54 PM PST 24
Peak memory 183768 kb
Host smart-42b5334b-ee9d-4473-b23c-92efc64b52de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602950780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2602950780
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3003527389
Short name T253
Test name
Test status
Simulation time 336479864 ps
CPU time 0.66 seconds
Started Jan 07 12:46:54 PM PST 24
Finished Jan 07 12:48:34 PM PST 24
Peak memory 183624 kb
Host smart-8bd0a805-fcc9-4d09-a43e-5744177d78ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003527389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3003527389
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.4086770276
Short name T255
Test name
Test status
Simulation time 401888338 ps
CPU time 0.65 seconds
Started Jan 07 12:46:24 PM PST 24
Finished Jan 07 12:48:33 PM PST 24
Peak memory 183468 kb
Host smart-1a75e5d4-b855-4b37-9e4d-673344b39b0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086770276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.4086770276
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1632287749
Short name T250
Test name
Test status
Simulation time 407913394 ps
CPU time 0.59 seconds
Started Jan 07 12:46:29 PM PST 24
Finished Jan 07 12:47:44 PM PST 24
Peak memory 183548 kb
Host smart-2060bab1-e08c-4acb-ace5-fc9d93f4c4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632287749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1632287749
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.95754743
Short name T290
Test name
Test status
Simulation time 312571160 ps
CPU time 1.01 seconds
Started Jan 07 12:46:54 PM PST 24
Finished Jan 07 12:48:27 PM PST 24
Peak memory 183536 kb
Host smart-67145203-e2ae-4314-b414-e06a41fb1622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95754743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.95754743
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1136811643
Short name T241
Test name
Test status
Simulation time 496904754 ps
CPU time 1.24 seconds
Started Jan 07 12:47:06 PM PST 24
Finished Jan 07 12:48:12 PM PST 24
Peak memory 183760 kb
Host smart-4b0eacfa-aa3d-40ec-b89b-f0f6bbd4ed4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136811643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1136811643
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.132239994
Short name T282
Test name
Test status
Simulation time 487504451 ps
CPU time 0.87 seconds
Started Jan 07 12:47:00 PM PST 24
Finished Jan 07 12:48:26 PM PST 24
Peak memory 183440 kb
Host smart-a5734e7a-f128-4f5d-99d7-8d1e5131d151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132239994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.132239994
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.337798077
Short name T248
Test name
Test status
Simulation time 465894138 ps
CPU time 0.58 seconds
Started Jan 07 12:46:24 PM PST 24
Finished Jan 07 12:48:33 PM PST 24
Peak memory 183440 kb
Host smart-766dd5a0-5057-4d90-932f-968dd9035c0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337798077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.337798077
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1375084999
Short name T59
Test name
Test status
Simulation time 7252674195 ps
CPU time 4.26 seconds
Started Jan 07 12:45:51 PM PST 24
Finished Jan 07 12:47:26 PM PST 24
Peak memory 195248 kb
Host smart-963c8902-29ad-46d3-a135-3e49c26eb369
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375084999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1375084999
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.315386778
Short name T34
Test name
Test status
Simulation time 1039323392 ps
CPU time 0.73 seconds
Started Jan 07 12:46:34 PM PST 24
Finished Jan 07 12:48:15 PM PST 24
Peak memory 183820 kb
Host smart-61bd853d-38c3-42bf-a780-35e2bc0e5d7e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315386778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.315386778
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1783818413
Short name T63
Test name
Test status
Simulation time 485093258 ps
CPU time 0.76 seconds
Started Jan 07 12:46:31 PM PST 24
Finished Jan 07 12:48:34 PM PST 24
Peak memory 183768 kb
Host smart-3b774b95-2b3b-42ff-b235-28886361d558
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783818413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1783818413
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.374005423
Short name T60
Test name
Test status
Simulation time 423683909 ps
CPU time 0.66 seconds
Started Jan 07 12:45:52 PM PST 24
Finished Jan 07 12:47:16 PM PST 24
Peak memory 183564 kb
Host smart-4d2a4e51-77eb-4857-af7e-2d9a240c440a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374005423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.374005423
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3956574463
Short name T249
Test name
Test status
Simulation time 426939597 ps
CPU time 0.63 seconds
Started Jan 07 12:45:51 PM PST 24
Finished Jan 07 12:47:25 PM PST 24
Peak memory 183548 kb
Host smart-f6e883b5-b816-4d71-9762-7def6e79f3fc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956574463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3956574463
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1120538937
Short name T309
Test name
Test status
Simulation time 488906146 ps
CPU time 0.68 seconds
Started Jan 07 12:45:59 PM PST 24
Finished Jan 07 12:47:36 PM PST 24
Peak memory 183428 kb
Host smart-8b1a3548-92b8-454e-9922-c15bee3819c8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120538937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1120538937
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1890518074
Short name T256
Test name
Test status
Simulation time 922052041 ps
CPU time 2.26 seconds
Started Jan 07 12:46:53 PM PST 24
Finished Jan 07 12:48:16 PM PST 24
Peak memory 198628 kb
Host smart-a179a20c-2c8b-4a4c-9018-30ddadfaea28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890518074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1890518074
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3342273890
Short name T64
Test name
Test status
Simulation time 292223308 ps
CPU time 0.63 seconds
Started Jan 07 12:46:34 PM PST 24
Finished Jan 07 12:48:13 PM PST 24
Peak memory 183564 kb
Host smart-8e3cfa2a-2f18-40f9-a81a-b90170e51286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342273890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3342273890
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.637747574
Short name T289
Test name
Test status
Simulation time 303824460 ps
CPU time 0.63 seconds
Started Jan 07 12:46:26 PM PST 24
Finished Jan 07 12:47:46 PM PST 24
Peak memory 183796 kb
Host smart-2d98fcdb-2427-4474-9b43-b55d25cddb2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637747574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.637747574
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.4140266923
Short name T259
Test name
Test status
Simulation time 277883456 ps
CPU time 0.7 seconds
Started Jan 07 12:47:07 PM PST 24
Finished Jan 07 12:48:17 PM PST 24
Peak memory 183424 kb
Host smart-d4a6a213-9a6c-4f64-93f3-560042b6dcf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140266923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.4140266923
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2900138553
Short name T298
Test name
Test status
Simulation time 371398709 ps
CPU time 0.55 seconds
Started Jan 07 12:46:17 PM PST 24
Finished Jan 07 12:48:34 PM PST 24
Peak memory 183484 kb
Host smart-24f8a579-949a-4cb2-a682-12f5c46ca06c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900138553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2900138553
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1786943744
Short name T284
Test name
Test status
Simulation time 447200916 ps
CPU time 1.25 seconds
Started Jan 07 12:46:42 PM PST 24
Finished Jan 07 12:47:55 PM PST 24
Peak memory 183536 kb
Host smart-dee0e28a-8c09-4afc-9220-01946994cd02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786943744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1786943744
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2910491334
Short name T278
Test name
Test status
Simulation time 525514978 ps
CPU time 0.6 seconds
Started Jan 07 12:46:52 PM PST 24
Finished Jan 07 12:48:18 PM PST 24
Peak memory 183768 kb
Host smart-9f94064f-6d78-4b73-8f64-1f08be03f34a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910491334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2910491334
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.4293829667
Short name T301
Test name
Test status
Simulation time 464614780 ps
CPU time 1.3 seconds
Started Jan 07 12:47:03 PM PST 24
Finished Jan 07 12:48:55 PM PST 24
Peak memory 183580 kb
Host smart-88aab313-583d-45b3-be1a-e42c644ecea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293829667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.4293829667
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1339088337
Short name T291
Test name
Test status
Simulation time 442082933 ps
CPU time 1.17 seconds
Started Jan 07 12:46:21 PM PST 24
Finished Jan 07 12:47:52 PM PST 24
Peak memory 183756 kb
Host smart-2f7e1deb-c44b-497a-85d6-7aa8bc435745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339088337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1339088337
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.6425042
Short name T263
Test name
Test status
Simulation time 376640513 ps
CPU time 0.83 seconds
Started Jan 07 12:46:51 PM PST 24
Finished Jan 07 12:48:34 PM PST 24
Peak memory 183396 kb
Host smart-0e41b05d-438d-4e17-8dbb-1f5d5fc8a874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6425042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.6425042
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.693019920
Short name T300
Test name
Test status
Simulation time 535069945 ps
CPU time 1.28 seconds
Started Jan 07 12:46:29 PM PST 24
Finished Jan 07 12:47:55 PM PST 24
Peak memory 194888 kb
Host smart-fbe2717c-be83-4a96-a19e-c06c4cdf5516
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693019920 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.693019920
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.514327255
Short name T74
Test name
Test status
Simulation time 421507682 ps
CPU time 1.09 seconds
Started Jan 07 12:46:26 PM PST 24
Finished Jan 07 12:47:51 PM PST 24
Peak memory 183860 kb
Host smart-03d3e099-98c1-4ef5-82f5-cc16b92e2c81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514327255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.514327255
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3880601595
Short name T271
Test name
Test status
Simulation time 425658427 ps
CPU time 1.2 seconds
Started Jan 07 12:46:35 PM PST 24
Finished Jan 07 12:47:52 PM PST 24
Peak memory 195588 kb
Host smart-f1c3f8c7-4ca6-4b01-ab21-bf5ba136c374
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880601595 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3880601595
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.468888840
Short name T56
Test name
Test status
Simulation time 442546994 ps
CPU time 0.71 seconds
Started Jan 07 12:46:30 PM PST 24
Finished Jan 07 12:48:12 PM PST 24
Peak memory 193128 kb
Host smart-144cc312-3e80-4ee5-8a0b-88ec74599f8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468888840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.468888840
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2225795959
Short name T288
Test name
Test status
Simulation time 1171548868 ps
CPU time 0.97 seconds
Started Jan 07 12:46:46 PM PST 24
Finished Jan 07 12:48:03 PM PST 24
Peak memory 194312 kb
Host smart-94554479-1f28-4a20-b3c0-e4144996e4bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225795959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2225795959
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.793059049
Short name T280
Test name
Test status
Simulation time 502055025 ps
CPU time 2.34 seconds
Started Jan 07 12:45:58 PM PST 24
Finished Jan 07 12:47:34 PM PST 24
Peak memory 198664 kb
Host smart-fa01de66-85f8-44bb-8c73-d6320bc62cc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793059049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.793059049
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2638709450
Short name T276
Test name
Test status
Simulation time 4489851414 ps
CPU time 2.66 seconds
Started Jan 07 12:46:24 PM PST 24
Finished Jan 07 12:48:44 PM PST 24
Peak memory 195828 kb
Host smart-4ce1bc81-2b69-4913-adce-5eef771d7381
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638709450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2638709450
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2343799124
Short name T68
Test name
Test status
Simulation time 472547227 ps
CPU time 1 seconds
Started Jan 07 12:46:08 PM PST 24
Finished Jan 07 12:48:29 PM PST 24
Peak memory 183772 kb
Host smart-aea7c28d-5796-4d0b-8c85-84688b1804c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343799124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2343799124
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3356241674
Short name T317
Test name
Test status
Simulation time 441298716 ps
CPU time 1.18 seconds
Started Jan 07 12:45:57 PM PST 24
Finished Jan 07 12:48:00 PM PST 24
Peak memory 183548 kb
Host smart-56108b47-d1fd-43df-8e88-7032d1e795b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356241674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3356241674
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2047054240
Short name T320
Test name
Test status
Simulation time 354970684 ps
CPU time 2.01 seconds
Started Jan 07 12:46:46 PM PST 24
Finished Jan 07 12:47:58 PM PST 24
Peak memory 198588 kb
Host smart-30d0ed41-a90f-4b04-b494-22038ea5045c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047054240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2047054240
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1228923452
Short name T103
Test name
Test status
Simulation time 8606743915 ps
CPU time 4.23 seconds
Started Jan 07 12:46:31 PM PST 24
Finished Jan 07 12:47:55 PM PST 24
Peak memory 197712 kb
Host smart-572750d9-1477-4986-8879-a2a244e65f66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228923452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1228923452
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2771220299
Short name T311
Test name
Test status
Simulation time 469298626 ps
CPU time 0.73 seconds
Started Jan 07 12:45:59 PM PST 24
Finished Jan 07 12:47:40 PM PST 24
Peak memory 183812 kb
Host smart-f179106b-dde4-48b1-b6fd-44bedf060934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771220299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2771220299
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2374921736
Short name T296
Test name
Test status
Simulation time 1239202679 ps
CPU time 1.03 seconds
Started Jan 07 12:46:33 PM PST 24
Finished Jan 07 12:47:58 PM PST 24
Peak memory 193436 kb
Host smart-d2d45cac-f9b3-4e8f-bbf0-1b0992b27b5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374921736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2374921736
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3016513952
Short name T239
Test name
Test status
Simulation time 413067726 ps
CPU time 2.04 seconds
Started Jan 07 12:46:39 PM PST 24
Finished Jan 07 12:48:21 PM PST 24
Peak memory 198676 kb
Host smart-33863312-7acd-4fae-b62b-8e1b6912be75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016513952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3016513952
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3183371806
Short name T28
Test name
Test status
Simulation time 362015924 ps
CPU time 0.69 seconds
Started Jan 07 12:46:44 PM PST 24
Finished Jan 07 12:48:34 PM PST 24
Peak memory 183668 kb
Host smart-a9101206-481b-4334-a460-019829e2d1c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183371806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3183371806
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1350625017
Short name T295
Test name
Test status
Simulation time 506688954 ps
CPU time 0.57 seconds
Started Jan 07 12:46:39 PM PST 24
Finished Jan 07 12:48:10 PM PST 24
Peak memory 183432 kb
Host smart-cf4cc0f9-f1fb-4aff-bf46-d55803f83d7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350625017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1350625017
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.20371036
Short name T78
Test name
Test status
Simulation time 1663354120 ps
CPU time 6.15 seconds
Started Jan 07 12:46:40 PM PST 24
Finished Jan 07 12:48:25 PM PST 24
Peak memory 195160 kb
Host smart-fa387fe4-8feb-449d-84bf-f72d8a5d01ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20371036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_t
imer_same_csr_outstanding.20371036
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2284394481
Short name T104
Test name
Test status
Simulation time 8452232073 ps
CPU time 4.48 seconds
Started Jan 07 12:46:32 PM PST 24
Finished Jan 07 12:47:50 PM PST 24
Peak memory 197596 kb
Host smart-7c1e8c91-2303-47b3-b1d3-193fcb06fee0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284394481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2284394481
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1350083858
Short name T96
Test name
Test status
Simulation time 359096054 ps
CPU time 1.09 seconds
Started Jan 07 12:43:31 PM PST 24
Finished Jan 07 12:44:32 PM PST 24
Peak memory 182576 kb
Host smart-1c631db2-4a74-4de2-8b2b-5e8064a1e0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350083858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1350083858
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.4103704578
Short name T149
Test name
Test status
Simulation time 104386458079 ps
CPU time 45.95 seconds
Started Jan 07 12:44:41 PM PST 24
Finished Jan 07 12:47:37 PM PST 24
Peak memory 182836 kb
Host smart-49b22783-7d6d-4bd7-bf3b-6d457f64f31f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103704578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.4103704578
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.138476379
Short name T73
Test name
Test status
Simulation time 553477261 ps
CPU time 1.29 seconds
Started Jan 07 12:44:03 PM PST 24
Finished Jan 07 12:45:22 PM PST 24
Peak memory 182664 kb
Host smart-45f6a67c-f519-4529-b21a-beb8f2c7e91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138476379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.138476379
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.445066863
Short name T46
Test name
Test status
Simulation time 19245778273 ps
CPU time 29.22 seconds
Started Jan 07 12:44:38 PM PST 24
Finished Jan 07 12:46:30 PM PST 24
Peak memory 182736 kb
Host smart-a6369723-30dd-408a-a45e-8f5102dc4f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445066863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.445066863
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2671064445
Short name T191
Test name
Test status
Simulation time 476033219 ps
CPU time 0.7 seconds
Started Jan 07 12:44:22 PM PST 24
Finished Jan 07 12:45:38 PM PST 24
Peak memory 182652 kb
Host smart-b218fc00-9ed4-4f71-829a-5cf03f530775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671064445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2671064445
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3368018726
Short name T144
Test name
Test status
Simulation time 516491633 ps
CPU time 1.39 seconds
Started Jan 07 12:44:49 PM PST 24
Finished Jan 07 12:46:45 PM PST 24
Peak memory 182716 kb
Host smart-01080f14-dda1-4adb-a8d7-217e8578b943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368018726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3368018726
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.643865351
Short name T43
Test name
Test status
Simulation time 55687801650 ps
CPU time 79.05 seconds
Started Jan 07 12:44:18 PM PST 24
Finished Jan 07 12:46:43 PM PST 24
Peak memory 182680 kb
Host smart-7045a6af-7211-4b3c-8ad7-0a2540486d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643865351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.643865351
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1724224341
Short name T97
Test name
Test status
Simulation time 407151823 ps
CPU time 1.07 seconds
Started Jan 07 12:44:16 PM PST 24
Finished Jan 07 12:45:45 PM PST 24
Peak memory 182612 kb
Host smart-6a55b253-b2be-4ae2-b461-82a2211bb0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724224341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1724224341
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1209917913
Short name T112
Test name
Test status
Simulation time 270213566792 ps
CPU time 232.73 seconds
Started Jan 07 12:44:41 PM PST 24
Finished Jan 07 12:50:04 PM PST 24
Peak memory 193144 kb
Host smart-19621d33-9432-4cd0-906d-c1d08e3af294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209917913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1209917913
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2946904550
Short name T48
Test name
Test status
Simulation time 202489880035 ps
CPU time 313.75 seconds
Started Jan 07 12:44:56 PM PST 24
Finished Jan 07 12:51:25 PM PST 24
Peak memory 197656 kb
Host smart-0b287ca4-c160-44fc-bd99-7c90c03e5d75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946904550 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2946904550
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1197737411
Short name T228
Test name
Test status
Simulation time 584379267 ps
CPU time 1.06 seconds
Started Jan 07 12:44:42 PM PST 24
Finished Jan 07 12:46:04 PM PST 24
Peak memory 182732 kb
Host smart-53676d39-af30-4736-b04b-7131afcab899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197737411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1197737411
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3921120384
Short name T166
Test name
Test status
Simulation time 34636175123 ps
CPU time 6.24 seconds
Started Jan 07 12:44:13 PM PST 24
Finished Jan 07 12:45:24 PM PST 24
Peak memory 182664 kb
Host smart-a7baa8b4-8249-467a-8c4b-1be2684047c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921120384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3921120384
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.4183147355
Short name T87
Test name
Test status
Simulation time 440560827 ps
CPU time 0.59 seconds
Started Jan 07 12:44:20 PM PST 24
Finished Jan 07 12:46:11 PM PST 24
Peak memory 182592 kb
Host smart-328f7c6e-76c2-4afd-90d3-3c77cacd26ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183147355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.4183147355
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1531652237
Short name T124
Test name
Test status
Simulation time 247293934703 ps
CPU time 361.19 seconds
Started Jan 07 12:44:58 PM PST 24
Finished Jan 07 12:52:14 PM PST 24
Peak memory 182696 kb
Host smart-674f7966-0fbe-43f6-a601-e28f2e33f35b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531652237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1531652237
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.478404272
Short name T141
Test name
Test status
Simulation time 386650112 ps
CPU time 0.78 seconds
Started Jan 07 12:44:40 PM PST 24
Finished Jan 07 12:46:13 PM PST 24
Peak memory 182716 kb
Host smart-0a1836aa-0ef1-4cc9-87bc-6110ef38513b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478404272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.478404272
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.342156145
Short name T177
Test name
Test status
Simulation time 9809689259 ps
CPU time 7.45 seconds
Started Jan 07 12:44:08 PM PST 24
Finished Jan 07 12:45:20 PM PST 24
Peak memory 182764 kb
Host smart-71d733d8-d992-4915-8c48-ba86a1901e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342156145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.342156145
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2327285574
Short name T132
Test name
Test status
Simulation time 388501974 ps
CPU time 0.61 seconds
Started Jan 07 12:44:53 PM PST 24
Finished Jan 07 12:46:28 PM PST 24
Peak memory 182532 kb
Host smart-77949cae-a4e9-456c-8d78-1723fb9cfd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327285574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2327285574
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1881251865
Short name T188
Test name
Test status
Simulation time 460031940 ps
CPU time 1.24 seconds
Started Jan 07 12:44:47 PM PST 24
Finished Jan 07 12:46:11 PM PST 24
Peak memory 182688 kb
Host smart-c5a0dec1-261d-4482-a512-5d7be7065cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881251865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1881251865
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2157553760
Short name T215
Test name
Test status
Simulation time 321886469746 ps
CPU time 136.81 seconds
Started Jan 07 12:44:30 PM PST 24
Finished Jan 07 12:48:03 PM PST 24
Peak memory 182716 kb
Host smart-93d50b3c-cb6e-4901-8eb9-1db4489ca081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157553760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2157553760
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3681311626
Short name T37
Test name
Test status
Simulation time 37853345814 ps
CPU time 140.76 seconds
Started Jan 07 12:44:43 PM PST 24
Finished Jan 07 12:48:25 PM PST 24
Peak memory 197688 kb
Host smart-ec6e8a9f-1b63-4fc1-8ffe-568017799305
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681311626 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3681311626
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3682356035
Short name T114
Test name
Test status
Simulation time 477564438 ps
CPU time 0.73 seconds
Started Jan 07 12:44:19 PM PST 24
Finished Jan 07 12:46:18 PM PST 24
Peak memory 182700 kb
Host smart-9e1c25a0-d5b8-4194-b88c-6ba9d62fee96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682356035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3682356035
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1891453877
Short name T178
Test name
Test status
Simulation time 25154936473 ps
CPU time 4.73 seconds
Started Jan 07 12:44:15 PM PST 24
Finished Jan 07 12:45:53 PM PST 24
Peak memory 182676 kb
Host smart-c3890137-4e42-496e-b0ba-71707fdc84e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891453877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1891453877
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2422329310
Short name T174
Test name
Test status
Simulation time 405940416 ps
CPU time 0.8 seconds
Started Jan 07 12:44:07 PM PST 24
Finished Jan 07 12:46:16 PM PST 24
Peak memory 182608 kb
Host smart-f7dacd08-33c9-4364-8c69-6b9774b67caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422329310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2422329310
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1472793064
Short name T23
Test name
Test status
Simulation time 85005243779 ps
CPU time 57.86 seconds
Started Jan 07 12:44:04 PM PST 24
Finished Jan 07 12:46:07 PM PST 24
Peak memory 182756 kb
Host smart-f4484fa8-73e5-42b9-9d9a-71d596b672e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472793064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1472793064
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2598918097
Short name T123
Test name
Test status
Simulation time 491684301 ps
CPU time 0.73 seconds
Started Jan 07 12:44:05 PM PST 24
Finished Jan 07 12:45:49 PM PST 24
Peak memory 182692 kb
Host smart-15ec919b-2cb7-4fdc-bcc5-fd5513fc6000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598918097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2598918097
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3741722522
Short name T86
Test name
Test status
Simulation time 2287403414 ps
CPU time 1.49 seconds
Started Jan 07 12:44:26 PM PST 24
Finished Jan 07 12:45:36 PM PST 24
Peak memory 182768 kb
Host smart-90fda668-dcb8-4f14-b2f3-450cc1fab947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741722522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3741722522
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1276229576
Short name T160
Test name
Test status
Simulation time 610289071 ps
CPU time 0.61 seconds
Started Jan 07 12:44:48 PM PST 24
Finished Jan 07 12:46:12 PM PST 24
Peak memory 182580 kb
Host smart-2e9f6fc8-9039-4c95-9490-48ad771d0aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276229576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1276229576
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1137642544
Short name T12
Test name
Test status
Simulation time 76372130046 ps
CPU time 21.21 seconds
Started Jan 07 12:44:23 PM PST 24
Finished Jan 07 12:45:59 PM PST 24
Peak memory 192960 kb
Host smart-7d6d25b1-b403-46a3-87f2-1b8bacd05c2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137642544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1137642544
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1206296200
Short name T190
Test name
Test status
Simulation time 605624607 ps
CPU time 0.57 seconds
Started Jan 07 12:44:20 PM PST 24
Finished Jan 07 12:45:32 PM PST 24
Peak memory 182732 kb
Host smart-bb63b3c5-5a09-4ab4-ac58-ecb38d49278e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206296200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1206296200
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3464989242
Short name T9
Test name
Test status
Simulation time 24843890332 ps
CPU time 35.92 seconds
Started Jan 07 12:44:47 PM PST 24
Finished Jan 07 12:46:49 PM PST 24
Peak memory 182768 kb
Host smart-871385a3-34a0-42be-aa77-0ff3957ff12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464989242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3464989242
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3697158545
Short name T155
Test name
Test status
Simulation time 389269108 ps
CPU time 0.66 seconds
Started Jan 07 12:44:19 PM PST 24
Finished Jan 07 12:45:29 PM PST 24
Peak memory 182528 kb
Host smart-0389d1b9-ada9-41e0-9965-a9cc1674e14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697158545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3697158545
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3504922098
Short name T156
Test name
Test status
Simulation time 171656124912 ps
CPU time 135.97 seconds
Started Jan 07 12:44:13 PM PST 24
Finished Jan 07 12:47:50 PM PST 24
Peak memory 193076 kb
Host smart-0cc58a94-8a66-40f3-9bed-bcec32a43626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504922098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3504922098
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.824736013
Short name T176
Test name
Test status
Simulation time 9743144650 ps
CPU time 95.12 seconds
Started Jan 07 12:44:10 PM PST 24
Finished Jan 07 12:47:12 PM PST 24
Peak memory 197580 kb
Host smart-f5ddd452-7b97-43c8-92dc-54c4a53d2461
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824736013 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.824736013
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2959280869
Short name T143
Test name
Test status
Simulation time 603322369 ps
CPU time 0.98 seconds
Started Jan 07 12:44:51 PM PST 24
Finished Jan 07 12:47:29 PM PST 24
Peak memory 182744 kb
Host smart-f15d0753-3c53-45ae-8f94-7781a768a8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959280869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2959280869
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1750225254
Short name T229
Test name
Test status
Simulation time 28361378282 ps
CPU time 11.44 seconds
Started Jan 07 12:44:38 PM PST 24
Finished Jan 07 12:46:14 PM PST 24
Peak memory 182784 kb
Host smart-d469b5dd-9c48-4c20-821d-2f1dae68e07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750225254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1750225254
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3898253982
Short name T140
Test name
Test status
Simulation time 352473154 ps
CPU time 0.85 seconds
Started Jan 07 12:44:48 PM PST 24
Finished Jan 07 12:46:10 PM PST 24
Peak memory 182736 kb
Host smart-f3792bd2-0e5b-4e66-9939-5ecdbbbc5a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898253982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3898253982
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1928368296
Short name T106
Test name
Test status
Simulation time 101244954831 ps
CPU time 161.95 seconds
Started Jan 07 12:44:46 PM PST 24
Finished Jan 07 12:49:16 PM PST 24
Peak memory 194092 kb
Host smart-a2e5bd5e-9421-4b73-8140-234199b2a6a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928368296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1928368296
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2236123773
Short name T195
Test name
Test status
Simulation time 521263474 ps
CPU time 0.76 seconds
Started Jan 07 12:44:55 PM PST 24
Finished Jan 07 12:46:28 PM PST 24
Peak memory 182700 kb
Host smart-e0666fcc-7c4a-4da0-95f2-4796d0da15c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236123773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2236123773
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2169647642
Short name T163
Test name
Test status
Simulation time 59252737979 ps
CPU time 48.17 seconds
Started Jan 07 12:44:10 PM PST 24
Finished Jan 07 12:46:22 PM PST 24
Peak memory 182728 kb
Host smart-12d20b9f-4bc2-4d5e-ba42-4650f8b01a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169647642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2169647642
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1104426318
Short name T133
Test name
Test status
Simulation time 436819809 ps
CPU time 1.15 seconds
Started Jan 07 12:44:23 PM PST 24
Finished Jan 07 12:46:03 PM PST 24
Peak memory 182484 kb
Host smart-37c4c02f-21bc-4cfa-84b7-4c8b4c292575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104426318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1104426318
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1882275175
Short name T127
Test name
Test status
Simulation time 333264625062 ps
CPU time 290.47 seconds
Started Jan 07 12:44:44 PM PST 24
Finished Jan 07 12:51:34 PM PST 24
Peak memory 182728 kb
Host smart-bfac9b2e-d0ff-440d-8d71-e8150d603b52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882275175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1882275175
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2498015838
Short name T22
Test name
Test status
Simulation time 449245048 ps
CPU time 1.22 seconds
Started Jan 07 12:44:36 PM PST 24
Finished Jan 07 12:46:37 PM PST 24
Peak memory 182708 kb
Host smart-7aca9032-e5be-49c2-998b-13494e926e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498015838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2498015838
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3306168101
Short name T238
Test name
Test status
Simulation time 11951992587 ps
CPU time 17.48 seconds
Started Jan 07 12:44:57 PM PST 24
Finished Jan 07 12:46:31 PM PST 24
Peak memory 182716 kb
Host smart-bba0c7f4-ca77-4df1-a704-829dd491e70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306168101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3306168101
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2890859151
Short name T27
Test name
Test status
Simulation time 562075640 ps
CPU time 1.43 seconds
Started Jan 07 12:44:34 PM PST 24
Finished Jan 07 12:46:54 PM PST 24
Peak memory 182644 kb
Host smart-b2f0f0e6-42ae-43a2-a476-f86e0128ca50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890859151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2890859151
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3613866904
Short name T108
Test name
Test status
Simulation time 137759443348 ps
CPU time 213.25 seconds
Started Jan 07 12:45:04 PM PST 24
Finished Jan 07 12:50:26 PM PST 24
Peak memory 182816 kb
Host smart-05f7a995-9713-4884-9221-4af2d1442fd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613866904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3613866904
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3246693841
Short name T225
Test name
Test status
Simulation time 389896050 ps
CPU time 0.8 seconds
Started Jan 07 12:44:02 PM PST 24
Finished Jan 07 12:45:29 PM PST 24
Peak memory 182676 kb
Host smart-63f904ba-39b9-4b3f-9aab-8a4a48792d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246693841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3246693841
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3163558408
Short name T26
Test name
Test status
Simulation time 5367158016 ps
CPU time 2.28 seconds
Started Jan 07 12:44:04 PM PST 24
Finished Jan 07 12:45:51 PM PST 24
Peak memory 182680 kb
Host smart-2b5f0f16-5820-43a7-a585-f7f419b555c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163558408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3163558408
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.719698146
Short name T19
Test name
Test status
Simulation time 4850741926 ps
CPU time 1.76 seconds
Started Jan 07 12:44:45 PM PST 24
Finished Jan 07 12:46:09 PM PST 24
Peak memory 214836 kb
Host smart-dd831a60-61fe-4106-8b0c-ba3cd2d8e617
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719698146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.719698146
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3455307739
Short name T202
Test name
Test status
Simulation time 376031230 ps
CPU time 0.67 seconds
Started Jan 07 12:44:21 PM PST 24
Finished Jan 07 12:45:49 PM PST 24
Peak memory 182636 kb
Host smart-7b91b277-d27a-452c-887f-55802ba7b796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455307739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3455307739
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.4182489723
Short name T109
Test name
Test status
Simulation time 151055146464 ps
CPU time 128.91 seconds
Started Jan 07 12:44:06 PM PST 24
Finished Jan 07 12:47:41 PM PST 24
Peak memory 192720 kb
Host smart-338a796b-ffc1-45ee-a7ce-63a3a448fee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182489723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.4182489723
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3359330385
Short name T182
Test name
Test status
Simulation time 85209056284 ps
CPU time 219.95 seconds
Started Jan 07 12:44:45 PM PST 24
Finished Jan 07 12:50:15 PM PST 24
Peak memory 197696 kb
Host smart-65175c68-58e1-4e8a-8e47-e1dd416e615f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359330385 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3359330385
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2568867581
Short name T142
Test name
Test status
Simulation time 54123194629 ps
CPU time 22.29 seconds
Started Jan 07 12:45:01 PM PST 24
Finished Jan 07 12:47:03 PM PST 24
Peak memory 182796 kb
Host smart-b513395d-977d-48b5-a1f9-379b31e53357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568867581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2568867581
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3795996419
Short name T138
Test name
Test status
Simulation time 382645193 ps
CPU time 1.05 seconds
Started Jan 07 12:44:25 PM PST 24
Finished Jan 07 12:46:15 PM PST 24
Peak memory 182596 kb
Host smart-ba787670-01a6-4694-bff8-e118a1e0b5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795996419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3795996419
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3622681418
Short name T11
Test name
Test status
Simulation time 46316550868 ps
CPU time 17.8 seconds
Started Jan 07 12:44:51 PM PST 24
Finished Jan 07 12:46:35 PM PST 24
Peak memory 182712 kb
Host smart-ac0aec11-916f-44ab-bef4-3315dceccba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622681418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3622681418
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3372965686
Short name T232
Test name
Test status
Simulation time 104233947696 ps
CPU time 760.45 seconds
Started Jan 07 12:44:57 PM PST 24
Finished Jan 07 12:58:54 PM PST 24
Peak memory 199908 kb
Host smart-ae4fab08-0a42-428e-b16f-dd7588be7b46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372965686 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3372965686
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.122805900
Short name T134
Test name
Test status
Simulation time 524835470 ps
CPU time 0.7 seconds
Started Jan 07 12:45:05 PM PST 24
Finished Jan 07 12:46:24 PM PST 24
Peak memory 182564 kb
Host smart-16c83adc-d7c5-4e33-b782-4c1afe3db651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122805900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.122805900
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3447521924
Short name T205
Test name
Test status
Simulation time 119278755255 ps
CPU time 44.04 seconds
Started Jan 07 12:44:16 PM PST 24
Finished Jan 07 12:46:05 PM PST 24
Peak memory 182688 kb
Host smart-13ae004e-2660-4a92-803d-7dcc69dfda9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447521924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3447521924
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3774997345
Short name T210
Test name
Test status
Simulation time 52402363516 ps
CPU time 298.64 seconds
Started Jan 07 12:44:23 PM PST 24
Finished Jan 07 12:50:51 PM PST 24
Peak memory 197588 kb
Host smart-b47d0dd9-fece-4b00-9483-025649ff7c14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774997345 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3774997345
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3781511933
Short name T4
Test name
Test status
Simulation time 476586941 ps
CPU time 1.3 seconds
Started Jan 07 12:44:48 PM PST 24
Finished Jan 07 12:46:12 PM PST 24
Peak memory 182664 kb
Host smart-e0651c25-ae67-4b77-b026-2e56509d6a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781511933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3781511933
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2272907896
Short name T117
Test name
Test status
Simulation time 68471998306 ps
CPU time 114.03 seconds
Started Jan 07 12:44:42 PM PST 24
Finished Jan 07 12:48:05 PM PST 24
Peak memory 192876 kb
Host smart-68f380cf-c5dd-4d9f-bd9a-1c79105d3c0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272907896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2272907896
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2913038609
Short name T180
Test name
Test status
Simulation time 254482314172 ps
CPU time 484.09 seconds
Started Jan 07 12:44:45 PM PST 24
Finished Jan 07 12:54:07 PM PST 24
Peak memory 197712 kb
Host smart-cc43a775-f7d8-4dfc-a0e6-0a1c528afc45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913038609 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2913038609
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1953041963
Short name T157
Test name
Test status
Simulation time 533796955 ps
CPU time 0.91 seconds
Started Jan 07 12:44:30 PM PST 24
Finished Jan 07 12:45:49 PM PST 24
Peak memory 182612 kb
Host smart-4ae3a729-19af-45b9-8c7e-345d73f39da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953041963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1953041963
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.319764315
Short name T154
Test name
Test status
Simulation time 10427927123 ps
CPU time 9.48 seconds
Started Jan 07 12:44:50 PM PST 24
Finished Jan 07 12:46:34 PM PST 24
Peak memory 182736 kb
Host smart-531aada4-a95a-4f64-8f3a-a106756628a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319764315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.319764315
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2283897277
Short name T3
Test name
Test status
Simulation time 562286783 ps
CPU time 0.71 seconds
Started Jan 07 12:44:21 PM PST 24
Finished Jan 07 12:45:27 PM PST 24
Peak memory 182724 kb
Host smart-98e4e2bb-e232-40d3-b6a2-cc29b01e9004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283897277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2283897277
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3825995360
Short name T115
Test name
Test status
Simulation time 530069331 ps
CPU time 0.65 seconds
Started Jan 07 12:44:58 PM PST 24
Finished Jan 07 12:46:33 PM PST 24
Peak memory 182752 kb
Host smart-76b8ab93-f144-45e4-ac6a-40ad862f1847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825995360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3825995360
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3373872687
Short name T72
Test name
Test status
Simulation time 47018087633 ps
CPU time 333.67 seconds
Started Jan 07 12:44:26 PM PST 24
Finished Jan 07 12:51:47 PM PST 24
Peak memory 197564 kb
Host smart-f0375909-f1eb-4a2e-9dc3-6330ae5912c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373872687 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3373872687
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2089418269
Short name T165
Test name
Test status
Simulation time 479053408 ps
CPU time 0.56 seconds
Started Jan 07 12:45:19 PM PST 24
Finished Jan 07 12:47:16 PM PST 24
Peak memory 182656 kb
Host smart-c4cf9166-aae1-49ec-a146-3a4357257633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089418269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2089418269
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2090731948
Short name T152
Test name
Test status
Simulation time 397394080 ps
CPU time 0.66 seconds
Started Jan 07 12:44:29 PM PST 24
Finished Jan 07 12:46:06 PM PST 24
Peak memory 182668 kb
Host smart-1c34fd77-3b18-4a59-989d-a9b2f1783150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090731948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2090731948
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3878001084
Short name T147
Test name
Test status
Simulation time 13904344700 ps
CPU time 142.03 seconds
Started Jan 07 12:45:15 PM PST 24
Finished Jan 07 12:49:31 PM PST 24
Peak memory 197616 kb
Host smart-a8b503a8-2374-4683-a0f3-37c81191f47a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878001084 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3878001084
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3258428349
Short name T170
Test name
Test status
Simulation time 626966985 ps
CPU time 0.77 seconds
Started Jan 07 12:44:58 PM PST 24
Finished Jan 07 12:46:14 PM PST 24
Peak memory 182708 kb
Host smart-18caadf7-ede2-4003-81bb-ac2727a2ef24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258428349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3258428349
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3592542267
Short name T169
Test name
Test status
Simulation time 34191156901 ps
CPU time 54.31 seconds
Started Jan 07 12:44:50 PM PST 24
Finished Jan 07 12:46:58 PM PST 24
Peak memory 182752 kb
Host smart-1fcbdfde-5864-42a9-b0a1-6e7ffd4edd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592542267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3592542267
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.4100736624
Short name T200
Test name
Test status
Simulation time 430268747 ps
CPU time 1.17 seconds
Started Jan 07 12:44:53 PM PST 24
Finished Jan 07 12:46:29 PM PST 24
Peak memory 182584 kb
Host smart-29002e8d-31f4-492e-8cc5-20dc119b5710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100736624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.4100736624
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2040132958
Short name T181
Test name
Test status
Simulation time 135527082750 ps
CPU time 206.45 seconds
Started Jan 07 12:45:10 PM PST 24
Finished Jan 07 12:50:08 PM PST 24
Peak memory 182712 kb
Host smart-e2190235-d39f-4dde-bd67-0071ccf4b150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040132958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2040132958
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3872586191
Short name T146
Test name
Test status
Simulation time 51173974951 ps
CPU time 73.38 seconds
Started Jan 07 12:45:11 PM PST 24
Finished Jan 07 12:47:44 PM PST 24
Peak memory 197592 kb
Host smart-8ae8f8f8-fad1-44c8-b691-3cb0d822df7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872586191 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3872586191
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2083296980
Short name T187
Test name
Test status
Simulation time 555668357 ps
CPU time 0.83 seconds
Started Jan 07 12:44:41 PM PST 24
Finished Jan 07 12:46:13 PM PST 24
Peak memory 182672 kb
Host smart-d163dbde-e596-451e-a666-3a99ec4e8323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083296980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2083296980
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3206708083
Short name T130
Test name
Test status
Simulation time 32811820871 ps
CPU time 47.58 seconds
Started Jan 07 12:44:48 PM PST 24
Finished Jan 07 12:47:21 PM PST 24
Peak memory 182700 kb
Host smart-f120e9de-0647-45b1-bf67-f52fa74be99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206708083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3206708083
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.4094629220
Short name T230
Test name
Test status
Simulation time 390568078 ps
CPU time 1.01 seconds
Started Jan 07 12:44:32 PM PST 24
Finished Jan 07 12:46:11 PM PST 24
Peak memory 182604 kb
Host smart-7869b302-083a-43bd-8180-262343d3a097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094629220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.4094629220
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.718649986
Short name T168
Test name
Test status
Simulation time 133000741531 ps
CPU time 198.13 seconds
Started Jan 07 12:44:56 PM PST 24
Finished Jan 07 12:49:45 PM PST 24
Peak memory 192984 kb
Host smart-8a5537d1-124b-4971-91ea-ee477be4df1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718649986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.718649986
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2472934943
Short name T211
Test name
Test status
Simulation time 216587431340 ps
CPU time 596.82 seconds
Started Jan 07 12:44:45 PM PST 24
Finished Jan 07 12:56:34 PM PST 24
Peak memory 198968 kb
Host smart-7c1e8858-4662-4243-bea2-7b56d1dc7933
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472934943 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2472934943
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2322775017
Short name T139
Test name
Test status
Simulation time 400918855 ps
CPU time 0.8 seconds
Started Jan 07 12:44:14 PM PST 24
Finished Jan 07 12:45:57 PM PST 24
Peak memory 182772 kb
Host smart-418c3e7f-d233-4a9b-91a7-24db3616cc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322775017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2322775017
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.411967909
Short name T129
Test name
Test status
Simulation time 17738663398 ps
CPU time 7.04 seconds
Started Jan 07 12:44:42 PM PST 24
Finished Jan 07 12:46:11 PM PST 24
Peak memory 182792 kb
Host smart-70c39259-74f8-4c3d-aeae-9abe3da850fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411967909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.411967909
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3956592012
Short name T135
Test name
Test status
Simulation time 416355028 ps
CPU time 0.88 seconds
Started Jan 07 12:44:41 PM PST 24
Finished Jan 07 12:46:10 PM PST 24
Peak memory 182712 kb
Host smart-40292342-5eb8-46c3-b3f8-6d11dc93df8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956592012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3956592012
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3928804260
Short name T172
Test name
Test status
Simulation time 83495423425 ps
CPU time 33.79 seconds
Started Jan 07 12:44:42 PM PST 24
Finished Jan 07 12:46:32 PM PST 24
Peak memory 182692 kb
Host smart-eddef3b8-c38e-4701-9243-b8ea32f48e86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928804260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3928804260
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2613901189
Short name T111
Test name
Test status
Simulation time 89959141888 ps
CPU time 486.44 seconds
Started Jan 07 12:45:00 PM PST 24
Finished Jan 07 12:54:44 PM PST 24
Peak memory 197900 kb
Host smart-574b7d48-3a44-4375-91e8-858eff24c759
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613901189 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2613901189
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2111401880
Short name T125
Test name
Test status
Simulation time 477533802 ps
CPU time 1.18 seconds
Started Jan 07 12:44:48 PM PST 24
Finished Jan 07 12:46:10 PM PST 24
Peak memory 182704 kb
Host smart-68025f69-3acb-48f4-9c76-297748157645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111401880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2111401880
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2391360213
Short name T47
Test name
Test status
Simulation time 44384960283 ps
CPU time 71.1 seconds
Started Jan 07 12:44:55 PM PST 24
Finished Jan 07 12:47:46 PM PST 24
Peak memory 182680 kb
Host smart-fb115701-6d1e-4e86-a679-157c44dd0857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391360213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2391360213
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.841295696
Short name T159
Test name
Test status
Simulation time 568565464 ps
CPU time 0.95 seconds
Started Jan 07 12:44:41 PM PST 24
Finished Jan 07 12:46:02 PM PST 24
Peak memory 182580 kb
Host smart-22c6f199-eb4f-4112-8b1f-b129308b3012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841295696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.841295696
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1468634609
Short name T208
Test name
Test status
Simulation time 202415509952 ps
CPU time 169.74 seconds
Started Jan 07 12:44:26 PM PST 24
Finished Jan 07 12:48:28 PM PST 24
Peak memory 192976 kb
Host smart-cb449d22-4917-42a8-9b19-b82bb6b4ee4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468634609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1468634609
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.334830635
Short name T145
Test name
Test status
Simulation time 592595420 ps
CPU time 0.74 seconds
Started Jan 07 12:44:07 PM PST 24
Finished Jan 07 12:45:48 PM PST 24
Peak memory 182660 kb
Host smart-908d644c-e47e-4b4b-a013-16b38e28043f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334830635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.334830635
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3581689025
Short name T10
Test name
Test status
Simulation time 29682631898 ps
CPU time 47.63 seconds
Started Jan 07 12:44:06 PM PST 24
Finished Jan 07 12:47:36 PM PST 24
Peak memory 182812 kb
Host smart-e674a725-8037-47ca-85d2-559ade83f2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581689025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3581689025
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.65566588
Short name T18
Test name
Test status
Simulation time 4457797388 ps
CPU time 4.29 seconds
Started Jan 07 12:44:06 PM PST 24
Finished Jan 07 12:45:33 PM PST 24
Peak memory 214744 kb
Host smart-154e1dc1-db1e-41da-b5a7-34fc3887aec0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65566588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.65566588
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2852993874
Short name T197
Test name
Test status
Simulation time 447063413 ps
CPU time 1.16 seconds
Started Jan 07 12:44:31 PM PST 24
Finished Jan 07 12:45:50 PM PST 24
Peak memory 182528 kb
Host smart-b0314583-dd0a-4096-9be8-0447102b71a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852993874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2852993874
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.289773262
Short name T69
Test name
Test status
Simulation time 164330504775 ps
CPU time 224.64 seconds
Started Jan 07 12:44:09 PM PST 24
Finished Jan 07 12:49:04 PM PST 24
Peak memory 182636 kb
Host smart-f768842b-0741-494e-86e1-0c0c0136d77f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289773262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.289773262
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.549004366
Short name T94
Test name
Test status
Simulation time 337301127053 ps
CPU time 657.04 seconds
Started Jan 07 12:44:06 PM PST 24
Finished Jan 07 12:56:15 PM PST 24
Peak memory 199072 kb
Host smart-ed3a9685-fe5d-45d0-b2cd-6dabd999f428
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549004366 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.549004366
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.4080778017
Short name T95
Test name
Test status
Simulation time 554305900 ps
CPU time 1.37 seconds
Started Jan 07 12:44:57 PM PST 24
Finished Jan 07 12:46:57 PM PST 24
Peak memory 182676 kb
Host smart-4f29d27d-e5e6-4901-9a43-483c53f006ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080778017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.4080778017
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3235547298
Short name T131
Test name
Test status
Simulation time 36467999900 ps
CPU time 53.68 seconds
Started Jan 07 12:44:29 PM PST 24
Finished Jan 07 12:47:10 PM PST 24
Peak memory 182728 kb
Host smart-30d11086-b3dc-4892-a51c-a83ec26a02d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235547298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3235547298
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1456560232
Short name T224
Test name
Test status
Simulation time 439909592 ps
CPU time 1.23 seconds
Started Jan 07 12:44:29 PM PST 24
Finished Jan 07 12:45:53 PM PST 24
Peak memory 182668 kb
Host smart-2ec07772-5a33-4317-a7c1-e000457d8f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456560232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1456560232
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2396703375
Short name T221
Test name
Test status
Simulation time 589628391 ps
CPU time 0.77 seconds
Started Jan 07 12:44:58 PM PST 24
Finished Jan 07 12:46:14 PM PST 24
Peak memory 182628 kb
Host smart-9a5b46cd-a31b-4574-81c2-a341f686dbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396703375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2396703375
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.458233404
Short name T148
Test name
Test status
Simulation time 59090400236 ps
CPU time 87.08 seconds
Started Jan 07 12:44:59 PM PST 24
Finished Jan 07 12:48:17 PM PST 24
Peak memory 182784 kb
Host smart-55c92efc-bde4-4581-9ae9-b716e94a9b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458233404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.458233404
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3531753344
Short name T162
Test name
Test status
Simulation time 123912864439 ps
CPU time 90.4 seconds
Started Jan 07 12:44:54 PM PST 24
Finished Jan 07 12:47:52 PM PST 24
Peak memory 182760 kb
Host smart-32816eac-2b68-4558-b094-e8c60f8a74ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531753344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3531753344
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1330443727
Short name T212
Test name
Test status
Simulation time 567003276 ps
CPU time 0.78 seconds
Started Jan 07 12:44:30 PM PST 24
Finished Jan 07 12:45:49 PM PST 24
Peak memory 182644 kb
Host smart-59c7b0f1-893a-47ba-a5d8-b450e0dd00ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330443727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1330443727
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.947887519
Short name T204
Test name
Test status
Simulation time 20940179693 ps
CPU time 15.59 seconds
Started Jan 07 12:45:28 PM PST 24
Finished Jan 07 12:47:20 PM PST 24
Peak memory 182680 kb
Host smart-ee20c711-6854-45cc-a367-a21e9a186b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947887519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.947887519
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2324132494
Short name T2
Test name
Test status
Simulation time 429363614 ps
CPU time 1.21 seconds
Started Jan 07 12:45:12 PM PST 24
Finished Jan 07 12:46:51 PM PST 24
Peak memory 182596 kb
Host smart-8dc72b0f-fc92-4bb6-9bf1-c9a919c8bf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324132494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2324132494
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1126771167
Short name T192
Test name
Test status
Simulation time 102182645430 ps
CPU time 34.25 seconds
Started Jan 07 12:44:45 PM PST 24
Finished Jan 07 12:46:37 PM PST 24
Peak memory 182824 kb
Host smart-22997345-eee9-488d-b338-d64f0c12b9b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126771167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1126771167
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1041204376
Short name T71
Test name
Test status
Simulation time 68992366098 ps
CPU time 512.76 seconds
Started Jan 07 12:44:50 PM PST 24
Finished Jan 07 12:54:49 PM PST 24
Peak memory 197732 kb
Host smart-d0ea3344-7e63-4083-afc4-de1054f82620
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041204376 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1041204376
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3192443628
Short name T216
Test name
Test status
Simulation time 50323063080 ps
CPU time 81.53 seconds
Started Jan 07 12:45:02 PM PST 24
Finished Jan 07 12:48:02 PM PST 24
Peak memory 182712 kb
Host smart-b876b75b-6b1d-4031-aafb-50767e0e1520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192443628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3192443628
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.80855104
Short name T21
Test name
Test status
Simulation time 566205338 ps
CPU time 0.73 seconds
Started Jan 07 12:45:11 PM PST 24
Finished Jan 07 12:47:26 PM PST 24
Peak memory 182640 kb
Host smart-8b0aff6d-09d6-4cfe-992d-9c741a41c22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80855104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.80855104
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2116466958
Short name T217
Test name
Test status
Simulation time 267390022893 ps
CPU time 74.66 seconds
Started Jan 07 12:44:38 PM PST 24
Finished Jan 07 12:47:22 PM PST 24
Peak memory 193060 kb
Host smart-861d0bef-023b-46e4-8a30-f71df8afeee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116466958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2116466958
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1278206039
Short name T153
Test name
Test status
Simulation time 459553724679 ps
CPU time 691.47 seconds
Started Jan 07 12:45:22 PM PST 24
Finished Jan 07 12:58:13 PM PST 24
Peak memory 199856 kb
Host smart-1f3bbbdc-231b-419f-ba31-66d04de21df6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278206039 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1278206039
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.4138099318
Short name T150
Test name
Test status
Simulation time 6695222638 ps
CPU time 11.28 seconds
Started Jan 07 12:45:07 PM PST 24
Finished Jan 07 12:46:59 PM PST 24
Peak memory 182788 kb
Host smart-06038a0d-703e-4a84-92a8-9fd1ffa530bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138099318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.4138099318
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3878800430
Short name T223
Test name
Test status
Simulation time 49429550994 ps
CPU time 80.84 seconds
Started Jan 07 12:45:08 PM PST 24
Finished Jan 07 12:48:27 PM PST 24
Peak memory 182752 kb
Host smart-66e5ce01-f720-4399-b01b-f27a442cb80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878800430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3878800430
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.760507273
Short name T5
Test name
Test status
Simulation time 439844997 ps
CPU time 1.16 seconds
Started Jan 07 12:45:04 PM PST 24
Finished Jan 07 12:46:57 PM PST 24
Peak memory 182588 kb
Host smart-c16ae649-ec1f-42e1-81db-85f326e3bc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760507273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.760507273
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2463051192
Short name T119
Test name
Test status
Simulation time 264912565253 ps
CPU time 98.93 seconds
Started Jan 07 12:45:22 PM PST 24
Finished Jan 07 12:49:05 PM PST 24
Peak memory 182776 kb
Host smart-10b8906f-202b-4551-a194-98c1e195d5a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463051192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2463051192
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.4266240715
Short name T237
Test name
Test status
Simulation time 254494373416 ps
CPU time 448.62 seconds
Started Jan 07 12:44:53 PM PST 24
Finished Jan 07 12:53:49 PM PST 24
Peak memory 197544 kb
Host smart-79b39ae7-41d5-4799-a2ed-d4842806f5e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266240715 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.4266240715
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3172325510
Short name T161
Test name
Test status
Simulation time 432853229 ps
CPU time 1.17 seconds
Started Jan 07 12:45:37 PM PST 24
Finished Jan 07 12:47:14 PM PST 24
Peak memory 182620 kb
Host smart-74e266c0-8e99-4417-8a9b-38e9502528a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172325510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3172325510
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1853970713
Short name T226
Test name
Test status
Simulation time 19406660557 ps
CPU time 13.55 seconds
Started Jan 07 12:45:35 PM PST 24
Finished Jan 07 12:48:05 PM PST 24
Peak memory 182752 kb
Host smart-5254b5fe-d584-4b69-bb46-3b83252d0498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853970713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1853970713
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3542287005
Short name T194
Test name
Test status
Simulation time 385739600 ps
CPU time 0.7 seconds
Started Jan 07 12:45:00 PM PST 24
Finished Jan 07 12:46:20 PM PST 24
Peak memory 182568 kb
Host smart-690dd235-d674-4fec-8a28-c276db5e9cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542287005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3542287005
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2481458157
Short name T122
Test name
Test status
Simulation time 81857048707 ps
CPU time 113.67 seconds
Started Jan 07 12:45:21 PM PST 24
Finished Jan 07 12:49:04 PM PST 24
Peak memory 194160 kb
Host smart-df172275-0918-4044-a7c0-3f493f312ba0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481458157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2481458157
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3018688533
Short name T40
Test name
Test status
Simulation time 275355171778 ps
CPU time 665.33 seconds
Started Jan 07 12:45:31 PM PST 24
Finished Jan 07 12:58:39 PM PST 24
Peak memory 199308 kb
Host smart-02b80fa8-08d1-4d72-9dd9-4e2415cbe1a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018688533 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3018688533
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2069065582
Short name T203
Test name
Test status
Simulation time 398084794 ps
CPU time 0.64 seconds
Started Jan 07 12:44:51 PM PST 24
Finished Jan 07 12:46:36 PM PST 24
Peak memory 182612 kb
Host smart-c1108379-3e21-44eb-8ba2-010c8c5cbb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069065582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2069065582
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.975192271
Short name T220
Test name
Test status
Simulation time 2415530682 ps
CPU time 1.51 seconds
Started Jan 07 12:45:09 PM PST 24
Finished Jan 07 12:46:34 PM PST 24
Peak memory 182772 kb
Host smart-5a0adfb2-216d-4727-b524-1a17e7c1915b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975192271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.975192271
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1125643278
Short name T231
Test name
Test status
Simulation time 166330777538 ps
CPU time 63.65 seconds
Started Jan 07 12:45:17 PM PST 24
Finished Jan 07 12:48:05 PM PST 24
Peak memory 182708 kb
Host smart-309318d7-7d90-4d80-881e-289be932210d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125643278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1125643278
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.81330761
Short name T50
Test name
Test status
Simulation time 104370287472 ps
CPU time 446.89 seconds
Started Jan 07 12:44:45 PM PST 24
Finished Jan 07 12:53:42 PM PST 24
Peak memory 197816 kb
Host smart-874206e2-85a3-4f2a-9d38-dccb9689dd84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81330761 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.81330761
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.42155309
Short name T193
Test name
Test status
Simulation time 74071646891 ps
CPU time 26.37 seconds
Started Jan 07 12:45:38 PM PST 24
Finished Jan 07 12:47:44 PM PST 24
Peak memory 192984 kb
Host smart-a9e4552b-50c2-49ad-ac9a-6c90c5b5ac1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42155309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_al
l.42155309
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2259871873
Short name T219
Test name
Test status
Simulation time 570093411 ps
CPU time 0.91 seconds
Started Jan 07 12:45:04 PM PST 24
Finished Jan 07 12:46:57 PM PST 24
Peak memory 182700 kb
Host smart-0b6525aa-5dd1-4d5f-ba5e-342cc66525e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259871873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2259871873
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.598437325
Short name T196
Test name
Test status
Simulation time 23685166865 ps
CPU time 17.47 seconds
Started Jan 07 12:45:17 PM PST 24
Finished Jan 07 12:47:09 PM PST 24
Peak memory 182776 kb
Host smart-0bfccf3d-72ce-4e16-a344-628376fa4783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598437325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.598437325
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.990708513
Short name T20
Test name
Test status
Simulation time 547264736 ps
CPU time 0.89 seconds
Started Jan 07 12:44:51 PM PST 24
Finished Jan 07 12:46:32 PM PST 24
Peak memory 182452 kb
Host smart-d4b1089e-63a9-4882-b603-69a1019f7f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990708513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.990708513
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2849474668
Short name T234
Test name
Test status
Simulation time 13401491888 ps
CPU time 5.39 seconds
Started Jan 07 12:45:27 PM PST 24
Finished Jan 07 12:47:35 PM PST 24
Peak memory 193140 kb
Host smart-b7a5e264-e20e-4952-bbc3-9ded029528f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849474668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2849474668
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.203180677
Short name T42
Test name
Test status
Simulation time 36357093031 ps
CPU time 280.17 seconds
Started Jan 07 12:45:01 PM PST 24
Finished Jan 07 12:51:10 PM PST 24
Peak memory 197648 kb
Host smart-89a76a31-95d5-44b7-b01f-96364ad8ddfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203180677 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.203180677
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3524226166
Short name T189
Test name
Test status
Simulation time 473595069 ps
CPU time 0.64 seconds
Started Jan 07 12:44:12 PM PST 24
Finished Jan 07 12:45:49 PM PST 24
Peak memory 182624 kb
Host smart-8245ec5a-27c4-452a-b3f2-7826bb3b64ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524226166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3524226166
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.4169449544
Short name T167
Test name
Test status
Simulation time 10239728567 ps
CPU time 3.8 seconds
Started Jan 07 12:44:19 PM PST 24
Finished Jan 07 12:46:31 PM PST 24
Peak memory 182724 kb
Host smart-78902ae9-bb66-4255-af19-310826348165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169449544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.4169449544
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.311275235
Short name T16
Test name
Test status
Simulation time 3888993995 ps
CPU time 3.77 seconds
Started Jan 07 12:43:52 PM PST 24
Finished Jan 07 12:45:51 PM PST 24
Peak memory 214552 kb
Host smart-fd967db8-d719-4dfe-81ea-6e8141c6a74f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311275235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.311275235
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3734359635
Short name T198
Test name
Test status
Simulation time 517711429 ps
CPU time 1.02 seconds
Started Jan 07 12:44:35 PM PST 24
Finished Jan 07 12:46:02 PM PST 24
Peak memory 182568 kb
Host smart-284a3b73-3ec3-4f88-a5c9-7f29b62e6e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734359635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3734359635
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1609979630
Short name T214
Test name
Test status
Simulation time 45837818155 ps
CPU time 379.65 seconds
Started Jan 07 12:44:16 PM PST 24
Finished Jan 07 12:51:59 PM PST 24
Peak memory 197640 kb
Host smart-df3e9d73-902d-45e9-9d9f-6405c2a40f71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609979630 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1609979630
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3718718605
Short name T222
Test name
Test status
Simulation time 21505517750 ps
CPU time 19.31 seconds
Started Jan 07 12:45:21 PM PST 24
Finished Jan 07 12:47:12 PM PST 24
Peak memory 182684 kb
Host smart-bbb23175-e331-45c8-a785-d850d4e472ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718718605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3718718605
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.686244089
Short name T38
Test name
Test status
Simulation time 85377600416 ps
CPU time 439.25 seconds
Started Jan 07 12:45:07 PM PST 24
Finished Jan 07 12:54:15 PM PST 24
Peak memory 197720 kb
Host smart-0d64d6b0-bc90-4e72-91a9-de2bc6fe434a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686244089 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.686244089
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.4227052311
Short name T98
Test name
Test status
Simulation time 537993686 ps
CPU time 1.33 seconds
Started Jan 07 12:45:09 PM PST 24
Finished Jan 07 12:47:17 PM PST 24
Peak memory 182760 kb
Host smart-8ddc6107-578c-4545-93c8-c8bff82d1138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227052311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.4227052311
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.443760057
Short name T235
Test name
Test status
Simulation time 41445552035 ps
CPU time 69.09 seconds
Started Jan 07 12:44:57 PM PST 24
Finished Jan 07 12:47:40 PM PST 24
Peak memory 182784 kb
Host smart-d2304383-1952-4c66-bd6f-1c0737dced21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443760057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.443760057
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2687012098
Short name T227
Test name
Test status
Simulation time 281302251896 ps
CPU time 110.81 seconds
Started Jan 07 12:44:56 PM PST 24
Finished Jan 07 12:48:31 PM PST 24
Peak memory 190980 kb
Host smart-edcef6f1-1fcc-4e9a-baea-b86af931f278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687012098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2687012098
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.48796225
Short name T183
Test name
Test status
Simulation time 486676819 ps
CPU time 0.67 seconds
Started Jan 07 12:45:22 PM PST 24
Finished Jan 07 12:46:51 PM PST 24
Peak memory 182736 kb
Host smart-50eb5d65-656f-4dd7-af2d-85bfa7896f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48796225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.48796225
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3100084211
Short name T137
Test name
Test status
Simulation time 11661501922 ps
CPU time 7.93 seconds
Started Jan 07 12:44:55 PM PST 24
Finished Jan 07 12:46:18 PM PST 24
Peak memory 182672 kb
Host smart-0cef1fc0-2624-46eb-9ff5-82511da313d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100084211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3100084211
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1179632913
Short name T92
Test name
Test status
Simulation time 226707709219 ps
CPU time 425.8 seconds
Started Jan 07 12:45:45 PM PST 24
Finished Jan 07 12:54:32 PM PST 24
Peak memory 197704 kb
Host smart-703766d8-3fc0-496c-a996-8065b80292ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179632913 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1179632913
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3630731646
Short name T184
Test name
Test status
Simulation time 531769910 ps
CPU time 1.48 seconds
Started Jan 07 12:45:16 PM PST 24
Finished Jan 07 12:47:09 PM PST 24
Peak memory 182636 kb
Host smart-21dacf7e-c90f-4552-8b18-856af924970c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630731646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3630731646
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1551536921
Short name T218
Test name
Test status
Simulation time 501855510 ps
CPU time 0.85 seconds
Started Jan 07 12:45:06 PM PST 24
Finished Jan 07 12:46:23 PM PST 24
Peak memory 182592 kb
Host smart-2010268c-6812-46b8-bb81-a7341f53cdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551536921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1551536921
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.438428241
Short name T128
Test name
Test status
Simulation time 207512221340 ps
CPU time 155.84 seconds
Started Jan 07 12:45:08 PM PST 24
Finished Jan 07 12:49:14 PM PST 24
Peak memory 192816 kb
Host smart-aecb0b98-705a-4654-86ac-afcc7774ddcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438428241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.438428241
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1273366885
Short name T118
Test name
Test status
Simulation time 604318701 ps
CPU time 0.77 seconds
Started Jan 07 12:45:20 PM PST 24
Finished Jan 07 12:46:53 PM PST 24
Peak memory 182704 kb
Host smart-2e0d55f1-9e6a-479d-b189-b17dbfc15031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273366885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1273366885
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2646360805
Short name T6
Test name
Test status
Simulation time 23186109796 ps
CPU time 10.48 seconds
Started Jan 07 12:44:55 PM PST 24
Finished Jan 07 12:46:38 PM PST 24
Peak memory 182716 kb
Host smart-a227b69b-44a4-4d5c-bff3-cf28180e563e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646360805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2646360805
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2270566311
Short name T206
Test name
Test status
Simulation time 560693163 ps
CPU time 0.7 seconds
Started Jan 07 12:45:39 PM PST 24
Finished Jan 07 12:47:38 PM PST 24
Peak memory 182596 kb
Host smart-afa6134c-b54e-4876-b948-2857197b1572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270566311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2270566311
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3083213949
Short name T164
Test name
Test status
Simulation time 114125589296 ps
CPU time 172.36 seconds
Started Jan 07 12:45:37 PM PST 24
Finished Jan 07 12:50:08 PM PST 24
Peak memory 182764 kb
Host smart-84bb7ca5-d3de-4598-99a8-49097ee29da7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083213949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3083213949
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2761385043
Short name T52
Test name
Test status
Simulation time 21936346282 ps
CPU time 79.19 seconds
Started Jan 07 12:45:18 PM PST 24
Finished Jan 07 12:48:28 PM PST 24
Peak memory 197624 kb
Host smart-b76c48b6-dcf0-4a86-8b33-91955e6b11f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761385043 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2761385043
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1045842934
Short name T186
Test name
Test status
Simulation time 544119056 ps
CPU time 0.69 seconds
Started Jan 07 12:45:23 PM PST 24
Finished Jan 07 12:47:16 PM PST 24
Peak memory 182772 kb
Host smart-b5dd1af9-5da8-44e0-a789-15dc23238d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045842934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1045842934
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2940647679
Short name T158
Test name
Test status
Simulation time 29618926983 ps
CPU time 11.41 seconds
Started Jan 07 12:45:09 PM PST 24
Finished Jan 07 12:46:58 PM PST 24
Peak memory 182848 kb
Host smart-37820930-24a5-4c15-8845-a407ea24f7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940647679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2940647679
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2339377017
Short name T201
Test name
Test status
Simulation time 410917999 ps
CPU time 0.68 seconds
Started Jan 07 12:45:19 PM PST 24
Finished Jan 07 12:47:06 PM PST 24
Peak memory 182640 kb
Host smart-a4d97452-86bb-47ec-bbb9-65e020d012a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339377017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2339377017
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2876778785
Short name T44
Test name
Test status
Simulation time 112143456139 ps
CPU time 189.02 seconds
Started Jan 07 12:45:37 PM PST 24
Finished Jan 07 12:50:09 PM PST 24
Peak memory 192856 kb
Host smart-af081510-3f44-4aea-81cc-11c959f94de8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876778785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2876778785
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2083684220
Short name T173
Test name
Test status
Simulation time 458081135 ps
CPU time 1.25 seconds
Started Jan 07 12:45:35 PM PST 24
Finished Jan 07 12:47:25 PM PST 24
Peak memory 182676 kb
Host smart-3fdc9afa-6f94-49c0-8038-b744639e73a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083684220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2083684220
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2230708863
Short name T185
Test name
Test status
Simulation time 38109750069 ps
CPU time 18.19 seconds
Started Jan 07 12:44:59 PM PST 24
Finished Jan 07 12:47:33 PM PST 24
Peak memory 182632 kb
Host smart-d2364b79-fda6-4842-9f06-957d5f742d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230708863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2230708863
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_jump.261884166
Short name T171
Test name
Test status
Simulation time 594604692 ps
CPU time 0.7 seconds
Started Jan 07 12:45:37 PM PST 24
Finished Jan 07 12:47:19 PM PST 24
Peak memory 182708 kb
Host smart-58b74498-d799-45ae-908d-5fe14a2db19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261884166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.261884166
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.57163306
Short name T1
Test name
Test status
Simulation time 386245257 ps
CPU time 0.61 seconds
Started Jan 07 12:45:01 PM PST 24
Finished Jan 07 12:46:39 PM PST 24
Peak memory 182640 kb
Host smart-b8fddc64-9b53-466f-8f6f-92fedb485175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57163306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.57163306
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3190243339
Short name T213
Test name
Test status
Simulation time 233201248338 ps
CPU time 192.29 seconds
Started Jan 07 12:45:05 PM PST 24
Finished Jan 07 12:50:28 PM PST 24
Peak memory 182716 kb
Host smart-da728563-4927-4567-b203-2f3aeb212d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190243339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3190243339
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1670652714
Short name T121
Test name
Test status
Simulation time 558123199 ps
CPU time 0.71 seconds
Started Jan 07 12:45:00 PM PST 24
Finished Jan 07 12:46:35 PM PST 24
Peak memory 182684 kb
Host smart-7d882420-f36f-4b6b-9b52-e9383439a7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670652714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1670652714
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2224311899
Short name T85
Test name
Test status
Simulation time 47094012309 ps
CPU time 23.87 seconds
Started Jan 07 12:44:56 PM PST 24
Finished Jan 07 12:46:39 PM PST 24
Peak memory 182632 kb
Host smart-1e2f3656-882f-4b9c-806c-d3c1728dd734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224311899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2224311899
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1284673509
Short name T209
Test name
Test status
Simulation time 527306847 ps
CPU time 0.68 seconds
Started Jan 07 12:45:09 PM PST 24
Finished Jan 07 12:46:40 PM PST 24
Peak memory 182604 kb
Host smart-b001ed96-7be8-479f-a322-fd551925407c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284673509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1284673509
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3892201473
Short name T105
Test name
Test status
Simulation time 211528935343 ps
CPU time 317.64 seconds
Started Jan 07 12:45:02 PM PST 24
Finished Jan 07 12:51:52 PM PST 24
Peak memory 182776 kb
Host smart-540bb493-3f5c-41d0-99a5-854f80f09ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892201473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3892201473
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1950407121
Short name T24
Test name
Test status
Simulation time 598632705 ps
CPU time 0.78 seconds
Started Jan 07 12:45:06 PM PST 24
Finished Jan 07 12:46:28 PM PST 24
Peak memory 182676 kb
Host smart-5e7e27f3-8205-4c25-8428-19592314c25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950407121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1950407121
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.4218080884
Short name T151
Test name
Test status
Simulation time 29007570129 ps
CPU time 12.16 seconds
Started Jan 07 12:45:05 PM PST 24
Finished Jan 07 12:47:24 PM PST 24
Peak memory 182728 kb
Host smart-7a2d1294-44b4-42f2-a199-faaf4891b114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218080884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.4218080884
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.593259044
Short name T136
Test name
Test status
Simulation time 409109074 ps
CPU time 0.68 seconds
Started Jan 07 12:45:03 PM PST 24
Finished Jan 07 12:46:47 PM PST 24
Peak memory 182644 kb
Host smart-4ef8217d-f0e6-40b5-abbe-052e3c7e380e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593259044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.593259044
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.4001987352
Short name T13
Test name
Test status
Simulation time 144408732149 ps
CPU time 186.86 seconds
Started Jan 07 12:45:30 PM PST 24
Finished Jan 07 12:50:40 PM PST 24
Peak memory 182848 kb
Host smart-753f2adb-e64b-4768-b0a3-b61f51d17904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001987352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.4001987352
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2581702355
Short name T36
Test name
Test status
Simulation time 47433914783 ps
CPU time 330.86 seconds
Started Jan 07 12:45:23 PM PST 24
Finished Jan 07 12:52:39 PM PST 24
Peak memory 197644 kb
Host smart-e5abb993-d0a2-449a-a47d-3c865062d566
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581702355 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2581702355
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2668573573
Short name T70
Test name
Test status
Simulation time 540500010 ps
CPU time 1.32 seconds
Started Jan 07 12:45:00 PM PST 24
Finished Jan 07 12:47:02 PM PST 24
Peak memory 182588 kb
Host smart-e7e7694e-367a-4ebc-99da-f09402541d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668573573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2668573573
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1474275202
Short name T207
Test name
Test status
Simulation time 10233181645 ps
CPU time 15.25 seconds
Started Jan 07 12:44:18 PM PST 24
Finished Jan 07 12:46:12 PM PST 24
Peak memory 182828 kb
Host smart-4f1edf3c-3626-46be-8de5-3230add39b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474275202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1474275202
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2227894689
Short name T179
Test name
Test status
Simulation time 130048894159 ps
CPU time 109.08 seconds
Started Jan 07 12:44:04 PM PST 24
Finished Jan 07 12:47:00 PM PST 24
Peak memory 193044 kb
Host smart-e1959a0f-e81d-4a57-840a-0d39f12e1cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227894689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2227894689
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1393585790
Short name T120
Test name
Test status
Simulation time 538785464 ps
CPU time 1.25 seconds
Started Jan 07 12:44:04 PM PST 24
Finished Jan 07 12:45:11 PM PST 24
Peak memory 182680 kb
Host smart-4ab17b3b-7955-46f4-a4bc-2b360bbe5095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393585790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1393585790
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1639604851
Short name T233
Test name
Test status
Simulation time 220876843395 ps
CPU time 151.7 seconds
Started Jan 07 12:44:10 PM PST 24
Finished Jan 07 12:48:11 PM PST 24
Peak memory 194044 kb
Host smart-90cf19bd-3061-4d01-9df9-9e7aeaf25785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639604851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1639604851
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2905442712
Short name T49
Test name
Test status
Simulation time 29927679462 ps
CPU time 206.56 seconds
Started Jan 07 12:44:39 PM PST 24
Finished Jan 07 12:49:31 PM PST 24
Peak memory 197700 kb
Host smart-b81d09a4-4f6f-4315-8e74-e9401f2bb185
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905442712 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2905442712
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.4148511165
Short name T236
Test name
Test status
Simulation time 485034260 ps
CPU time 0.72 seconds
Started Jan 07 12:43:55 PM PST 24
Finished Jan 07 12:45:37 PM PST 24
Peak memory 182708 kb
Host smart-96355357-49ba-4b65-9470-82e055c99d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148511165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.4148511165
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.4110021881
Short name T25
Test name
Test status
Simulation time 460370350 ps
CPU time 0.77 seconds
Started Jan 07 12:43:54 PM PST 24
Finished Jan 07 12:45:11 PM PST 24
Peak memory 182552 kb
Host smart-59802b9d-02fb-4b1d-8acb-ac77fb24ab4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110021881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.4110021881
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_jump.236073962
Short name T199
Test name
Test status
Simulation time 494650270 ps
CPU time 1.32 seconds
Started Jan 07 12:44:21 PM PST 24
Finished Jan 07 12:45:46 PM PST 24
Peak memory 182688 kb
Host smart-6480fd71-0319-4671-8b3c-030087d5c15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236073962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.236073962
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1706036569
Short name T88
Test name
Test status
Simulation time 38293875719 ps
CPU time 53.71 seconds
Started Jan 07 12:43:50 PM PST 24
Finished Jan 07 12:46:31 PM PST 24
Peak memory 182748 kb
Host smart-cf756a74-b10e-433e-988b-365463f8041c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706036569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1706036569
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3156896062
Short name T113
Test name
Test status
Simulation time 71317498227 ps
CPU time 31.42 seconds
Started Jan 07 12:44:47 PM PST 24
Finished Jan 07 12:47:01 PM PST 24
Peak memory 192944 kb
Host smart-f7722b94-197c-4f87-aa7f-37238ae7d20e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156896062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3156896062
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3329551569
Short name T45
Test name
Test status
Simulation time 507145229 ps
CPU time 0.71 seconds
Started Jan 07 12:44:14 PM PST 24
Finished Jan 07 12:45:35 PM PST 24
Peak memory 182616 kb
Host smart-ad8b5577-e38c-46b0-a974-b08d10bde3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329551569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3329551569
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.824035902
Short name T51
Test name
Test status
Simulation time 354251574 ps
CPU time 1.12 seconds
Started Jan 07 12:44:50 PM PST 24
Finished Jan 07 12:46:13 PM PST 24
Peak memory 182552 kb
Host smart-fac41e3b-e8d8-4e33-a5be-624382fa6cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824035902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.824035902
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3352387589
Short name T175
Test name
Test status
Simulation time 323941373003 ps
CPU time 454.01 seconds
Started Jan 07 12:44:48 PM PST 24
Finished Jan 07 12:53:40 PM PST 24
Peak memory 194180 kb
Host smart-6f79f0a5-bd8f-4f86-a003-711209b48b01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352387589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3352387589
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.373453370
Short name T89
Test name
Test status
Simulation time 49255312767 ps
CPU time 422.69 seconds
Started Jan 07 12:44:08 PM PST 24
Finished Jan 07 12:52:31 PM PST 24
Peak memory 197556 kb
Host smart-b4c14e19-ee1c-4faf-acf1-4b50bfc69383
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373453370 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.373453370
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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