Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	362911	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4840615	1		T1	9		T2	107		T6	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1291673	1		T1	9		T2	90		T6	6
values[0x0]	1845170	1		T1	10		T2	61		T6	5
values[0x1]	2066683	1		T1	7		T2	54		T6	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	165131	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5038395	1		T1	13		T2	133		T6	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18795	1		T1	1		T16	1		T17	1
valid_sources[0x01]	20641	1		T2	1		T13	1		T16	14
valid_sources[0x02]	21094	1		T2	1		T13	4		T16	2
valid_sources[0x03]	20678	1		T13	3		T16	3		T7	1
valid_sources[0x04]	20100	1		T2	2		T13	1		T4	5
valid_sources[0x05]	21415	1		T13	2		T3	5		T16	4
valid_sources[0x06]	20525	1		T13	1		T16	10		T17	2
valid_sources[0x07]	19455	1		T2	3		T16	4		T18	1
valid_sources[0x08]	20130	1		T13	2		T16	4		T18	2
valid_sources[0x09]	18708	1		T13	1		T3	3		T16	4
valid_sources[0x0a]	19318	1		T13	1		T16	5		T18	1
valid_sources[0x0b]	18574	1		T13	5		T15	1		T16	4
valid_sources[0x0c]	19364	1		T2	1		T13	2		T4	7
valid_sources[0x0d]	20288	1		T2	1		T13	1		T16	4
valid_sources[0x0e]	19994	1		T13	1		T3	1		T16	6
valid_sources[0x0f]	20844	1		T13	1		T16	11		T17	1
valid_sources[0x10]	20881	1		T2	1		T3	2		T16	5
valid_sources[0x11]	20183	1		T16	7		T17	2		T18	3
valid_sources[0x12]	21742	1		T2	1		T13	1		T16	9
valid_sources[0x13]	20050	1		T13	2		T16	5		T17	3
valid_sources[0x14]	20485	1		T2	2		T13	1		T17	2
valid_sources[0x15]	19408	1		T2	1		T3	13		T16	10
valid_sources[0x16]	20619	1		T2	1		T15	1		T16	6
valid_sources[0x17]	21194	1		T2	3		T13	5		T4	10
valid_sources[0x18]	20708	1		T13	2		T3	4		T15	1
valid_sources[0x19]	19700	1		T13	3		T16	2		T18	1
valid_sources[0x1a]	20197	1		T2	1		T13	1		T3	1
valid_sources[0x1b]	19984	1		T2	2		T13	1		T16	4
valid_sources[0x1c]	20304	1		T2	3		T13	2		T16	12
valid_sources[0x1d]	19401	1		T2	1		T13	1		T16	5
valid_sources[0x1e]	20208	1		T14	1		T16	5		T18	1
valid_sources[0x1f]	19804	1		T13	2		T16	6		T18	2
valid_sources[0x20]	20330	1		T13	4		T3	7		T16	5
valid_sources[0x21]	21551	1		T13	1		T16	4		T17	1
valid_sources[0x22]	19663	1		T2	1		T14	1		T3	4
valid_sources[0x23]	19518	1		T2	2		T3	10		T16	13
valid_sources[0x24]	19287	1		T2	1		T15	2		T16	12
valid_sources[0x25]	19776	1		T2	1		T13	2		T15	2
valid_sources[0x26]	20148	1		T2	2		T13	3		T14	1
valid_sources[0x27]	21314	1		T13	3		T16	9		T18	1
valid_sources[0x28]	20491	1		T2	1		T13	2		T16	18
valid_sources[0x29]	20931	1		T13	2		T16	3		T17	3
valid_sources[0x2a]	21635	1		T13	4		T15	1		T16	7
valid_sources[0x2b]	19357	1		T13	1		T3	4		T16	7
valid_sources[0x2c]	21690	1		T2	1		T13	5		T3	1
valid_sources[0x2d]	20237	1		T2	2		T13	5		T14	1
valid_sources[0x2e]	20152	1		T2	1		T13	5		T16	9
valid_sources[0x2f]	20280	1		T13	2		T15	1		T16	9
valid_sources[0x30]	21808	1		T2	1		T3	1		T16	14
valid_sources[0x31]	22828	1		T16	9		T17	3		T18	1
valid_sources[0x32]	19642	1		T2	1		T14	1		T16	9
valid_sources[0x33]	20110	1		T2	1		T13	4		T16	13
valid_sources[0x34]	20313	1		T16	14		T17	1		T18	3
valid_sources[0x35]	20630	1		T2	2		T13	1		T14	1
valid_sources[0x36]	19207	1		T13	2		T16	6		T17	1
valid_sources[0x37]	19632	1		T13	1		T3	7		T16	11
valid_sources[0x38]	21728	1		T2	1		T3	4		T16	7
valid_sources[0x39]	19525	1		T13	2		T16	13		T18	1
valid_sources[0x3a]	20887	1		T2	2		T13	2		T3	3
valid_sources[0x3b]	20554	1		T13	4		T3	1		T16	5
valid_sources[0x3c]	20326	1		T2	2		T3	6		T16	11
valid_sources[0x3d]	19977	1		T2	2		T13	1		T16	18
valid_sources[0x3e]	20552	1		T2	1		T13	2		T16	3
valid_sources[0x3f]	19790	1		T13	4		T3	1		T16	3
valid_sources[0x40]	21178	1		T2	1		T13	1		T16	4
valid_sources[0x41]	21041	1		T13	1		T14	1		T16	5
valid_sources[0x42]	19657	1		T2	1		T16	9		T17	2
valid_sources[0x43]	20625	1		T2	3		T13	1		T14	1
valid_sources[0x44]	20760	1		T13	1		T15	1		T16	8
valid_sources[0x45]	21015	1		T13	1		T16	17		T17	1
valid_sources[0x46]	20665	1		T2	1		T13	4		T3	3
valid_sources[0x47]	19225	1		T2	1		T13	7		T15	2
valid_sources[0x48]	19919	1		T13	4		T16	9		T18	2
valid_sources[0x49]	21601	1		T16	9		T17	1		T18	1
valid_sources[0x4a]	21157	1		T2	1		T13	1		T16	7
valid_sources[0x4b]	19746	1		T2	1		T13	2		T16	7
valid_sources[0x4c]	19191	1		T2	2		T13	2		T16	9
valid_sources[0x4d]	19703	1		T2	1		T13	2		T15	2
valid_sources[0x4e]	19922	1		T3	2		T15	3		T16	13
valid_sources[0x4f]	20327	1		T16	7		T17	2		T18	2
valid_sources[0x50]	20927	1		T2	1		T13	1		T16	6
valid_sources[0x51]	19656	1		T13	1		T3	3		T4	2
valid_sources[0x52]	20173	1		T13	1		T3	2		T15	1
valid_sources[0x53]	21100	1		T13	1		T15	2		T16	9
valid_sources[0x54]	20221	1		T2	2		T16	7		T18	2
valid_sources[0x55]	19609	1		T2	2		T4	4		T15	1
valid_sources[0x56]	21736	1		T13	3		T3	2		T15	1
valid_sources[0x57]	21872	1		T13	4		T16	3		T18	1
valid_sources[0x58]	21848	1		T13	3		T3	2		T16	6
valid_sources[0x59]	19293	1		T2	2		T13	1		T17	1
valid_sources[0x5a]	19800	1		T2	1		T13	4		T16	5
valid_sources[0x5b]	20710	1		T2	3		T13	3		T3	11
valid_sources[0x5c]	19357	1		T15	1		T16	8		T17	1
valid_sources[0x5d]	20022	1		T16	13		T17	2		T18	2
valid_sources[0x5e]	20451	1		T2	1		T13	1		T16	11
valid_sources[0x5f]	19217	1		T2	1		T13	4		T14	1
valid_sources[0x60]	20683	1		T13	3		T16	2		T17	1
valid_sources[0x61]	19926	1		T16	6		T17	1		T18	4
valid_sources[0x62]	19876	1		T2	1		T13	5		T16	5
valid_sources[0x63]	20737	1		T2	1		T13	3		T16	10
valid_sources[0x64]	21174	1		T16	8		T18	1		T7	2
valid_sources[0x65]	20250	1		T16	8		T18	1		T7	1
valid_sources[0x66]	20668	1		T2	1		T16	2		T17	1
valid_sources[0x67]	21101	1		T2	1		T13	1		T16	5
valid_sources[0x68]	18800	1		T1	1		T2	1		T13	4
valid_sources[0x69]	19417	1		T4	1		T16	9		T17	2
valid_sources[0x6a]	20455	1		T2	2		T13	4		T3	3
valid_sources[0x6b]	20079	1		T13	2		T16	9		T17	1
valid_sources[0x6c]	20260	1		T2	1		T13	1		T3	1
valid_sources[0x6d]	19967	1		T13	2		T4	2		T16	4
valid_sources[0x6e]	20424	1		T2	1		T13	3		T16	4
valid_sources[0x6f]	20758	1		T2	1		T13	3		T3	1
valid_sources[0x70]	20714	1		T13	2		T16	10		T17	3
valid_sources[0x71]	19880	1		T2	1		T13	5		T3	4
valid_sources[0x72]	20736	1		T2	1		T13	1		T16	6
valid_sources[0x73]	20566	1		T2	1		T13	1		T16	3
valid_sources[0x74]	20599	1		T2	4		T16	10		T17	1
valid_sources[0x75]	21256	1		T13	1		T4	15		T16	10
valid_sources[0x76]	20353	1		T2	1		T13	4		T3	1
valid_sources[0x77]	21484	1		T1	5		T2	1		T4	1
valid_sources[0x78]	20377	1		T2	1		T16	14		T22	3
valid_sources[0x79]	20818	1		T2	1		T13	5		T16	8
valid_sources[0x7a]	19187	1		T2	1		T13	2		T16	16
valid_sources[0x7b]	18857	1		T13	1		T4	14		T16	9
valid_sources[0x7c]	21167	1		T1	1		T2	1		T6	9
valid_sources[0x7d]	20541	1		T2	1		T13	1		T16	5
valid_sources[0x7e]	20259	1		T2	1		T13	2		T3	1
valid_sources[0x7f]	21288	1		T2	1		T13	1		T16	5
valid_sources[0x80]	20961	1		T2	2		T13	2		T16	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1211026

1

T1

1

T2

29

T6

4

values[0x0]

all_enables

biggest_size

1814993

1

T1

5

T2

43

T6

1

values[0x1]

all_enables

biggest_size

1814596

1

T1

3

T2

35

T13

155