Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	703709803	6844643	0	0
wdog_bark_thold_rd_A	703709803	112213	0	0
wdog_bite_thold_rd_A	703709803	98264	0	0
wdog_ctrl_rd_A	703709803	97886	0	0
wdog_regwen_rd_A	703709803	111566	0	0
wkup_ctrl_rd_A	703709803	97525	0	0
wkup_thold_rd_A	703709803	111458	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	6844643	0	0
T2	409333	3	0	0
T3	56754	0	0	0
T4	28968	0	0	0
T6	45174	0	0	0
T7	0	3	0	0
T9	0	55	0	0
T13	17781	560	0	0
T14	17500	0	0	0
T15	36887	2	0	0
T16	245862	0	0	0
T17	7582	527	0	0
T18	33555	244	0	0
T45	0	2	0	0
T47	0	421	0	0
T48	0	345	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	112213	0	0
T3	56754	0	0	0
T4	28968	0	0	0
T5	59157	68	0	0
T7	420647	0	0	0
T13	17781	25	0	0
T14	17500	0	0	0
T15	36887	0	0	0
T16	245862	0	0	0
T17	7582	0	0	0
T18	33555	46	0	0
T39	0	3096	0	0
T48	0	33	0	0
T49	0	22	0	0
T66	0	6572	0	0
T67	0	4463	0	0
T68	0	7323	0	0
T69	0	3136	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	98264	0	0
T3	56754	0	0	0
T4	28968	0	0	0
T5	59157	55	0	0
T7	420647	0	0	0
T13	17781	19	0	0
T14	17500	0	0	0
T15	36887	0	0	0
T16	245862	0	0	0
T17	7582	0	0	0
T18	33555	25	0	0
T39	0	2688	0	0
T48	0	16	0	0
T49	0	5	0	0
T66	0	6334	0	0
T67	0	3933	0	0
T68	0	6269	0	0
T69	0	2929	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	97886	0	0
T3	56754	0	0	0
T4	28968	0	0	0
T5	59157	31	0	0
T7	420647	0	0	0
T13	17781	24	0	0
T14	17500	0	0	0
T15	36887	0	0	0
T16	245862	0	0	0
T17	7582	0	0	0
T18	33555	42	0	0
T39	0	2691	0	0
T48	0	6	0	0
T49	0	10	0	0
T66	0	5676	0	0
T67	0	3482	0	0
T68	0	6351	0	0
T69	0	3200	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	111566	0	0
T3	56754	0	0	0
T4	28968	0	0	0
T5	59157	42	0	0
T7	420647	0	0	0
T13	17781	14	0	0
T14	17500	0	0	0
T15	36887	0	0	0
T16	245862	0	0	0
T17	7582	0	0	0
T18	33555	35	0	0
T39	0	3117	0	0
T48	0	33	0	0
T49	0	8	0	0
T66	0	6310	0	0
T67	0	4225	0	0
T68	0	6559	0	0
T69	0	3351	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	97525	0	0
T3	56754	0	0	0
T4	28968	0	0	0
T5	59157	66	0	0
T7	420647	0	0	0
T13	17781	16	0	0
T14	17500	0	0	0
T15	36887	0	0	0
T16	245862	0	0	0
T17	7582	0	0	0
T18	33555	38	0	0
T39	0	2927	0	0
T48	0	25	0	0
T49	0	24	0	0
T66	0	5726	0	0
T67	0	3633	0	0
T68	0	6242	0	0
T69	0	2835	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	703709803	111458	0	0
T3	56754	0	0	0
T4	28968	0	0	0
T5	59157	35	0	0
T7	420647	0	0	0
T13	17781	23	0	0
T14	17500	0	0	0
T15	36887	0	0	0
T16	245862	0	0	0
T17	7582	0	0	0
T18	33555	32	0	0
T39	0	3129	0	0
T48	0	27	0	0
T49	0	16	0	0
T66	0	6457	0	0
T67	0	4223	0	0
T68	0	7433	0	0
T69	0	3483	0	0