Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	374149	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4982482	1		T1	211		T2	217		T7	19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1329847	1		T1	167		T2	88		T7	13
values[0x0]	1899269	1		T1	122		T2	68		T7	9
values[0x1]	2127515	1		T1	129		T2	62		T7	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	169704	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5186927	1		T1	258		T2	217		T7	21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20539	1		T1	2		T12	1		T3	1
valid_sources[0x01]	22140	1		T1	3		T12	4		T8	2
valid_sources[0x02]	19828	1		T1	2		T12	1		T4	2
valid_sources[0x03]	21899	1		T1	4		T12	1		T8	2
valid_sources[0x04]	20893	1		T1	2		T12	2		T14	2
valid_sources[0x05]	20923	1		T12	1		T8	2		T23	5
valid_sources[0x06]	20608	1		T12	11		T14	1		T8	3
valid_sources[0x07]	21857	1		T12	1		T14	7		T8	2
valid_sources[0x08]	22848	1		T1	2		T12	9		T3	1
valid_sources[0x09]	20049	1		T1	2		T8	2		T9	1
valid_sources[0x0a]	20160	1		T1	1		T12	12		T8	2
valid_sources[0x0b]	21642	1		T1	3		T12	3		T14	13
valid_sources[0x0c]	20880	1		T1	3		T12	6		T8	4
valid_sources[0x0d]	19004	1		T1	1		T12	2		T8	4
valid_sources[0x0e]	21149	1		T1	1		T2	2		T8	2
valid_sources[0x0f]	19752	1		T12	3		T8	1		T4	2
valid_sources[0x10]	19591	1		T1	1		T12	17		T4	1
valid_sources[0x11]	20008	1		T12	6		T8	1		T4	1
valid_sources[0x12]	21682	1		T1	4		T8	1		T4	1
valid_sources[0x13]	20239	1		T1	1		T8	2		T9	2
valid_sources[0x14]	21773	1		T1	2		T23	21		T9	3
valid_sources[0x15]	20250	1		T1	1		T12	3		T8	3
valid_sources[0x16]	20637	1		T12	3		T14	15		T8	2
valid_sources[0x17]	22119	1		T1	1		T2	3		T12	1
valid_sources[0x18]	20639	1		T1	5		T8	5		T4	1
valid_sources[0x19]	19491	1		T1	4		T8	2		T5	1
valid_sources[0x1a]	22541	1		T1	3		T12	14		T14	5
valid_sources[0x1b]	20227	1		T1	1		T14	1		T4	2
valid_sources[0x1c]	21085	1		T1	1		T12	4		T14	4
valid_sources[0x1d]	20594	1		T1	3		T12	4		T8	2
valid_sources[0x1e]	19618	1		T1	2		T7	7		T12	12
valid_sources[0x1f]	21714	1		T12	12		T4	1		T9	4
valid_sources[0x20]	21378	1		T1	1		T12	2		T3	3
valid_sources[0x21]	21576	1		T12	4		T8	1		T4	1
valid_sources[0x22]	20212	1		T1	2		T12	1		T14	2
valid_sources[0x23]	22332	1		T1	1		T14	13		T8	4
valid_sources[0x24]	23918	1		T12	1		T5	3		T6	1
valid_sources[0x25]	20887	1		T1	1		T12	1		T14	8
valid_sources[0x26]	20739	1		T1	2		T4	1		T23	1
valid_sources[0x27]	21944	1		T1	1		T12	3		T14	14
valid_sources[0x28]	20646	1		T1	2		T8	4		T6	1
valid_sources[0x29]	21327	1		T1	1		T12	1		T13	55
valid_sources[0x2a]	21052	1		T12	4		T8	1		T4	1
valid_sources[0x2b]	20441	1		T1	4		T12	9		T8	3
valid_sources[0x2c]	21037	1		T1	1		T12	4		T13	57
valid_sources[0x2d]	19316	1		T1	1		T8	3		T4	1
valid_sources[0x2e]	20752	1		T1	1		T12	1		T14	6
valid_sources[0x2f]	19810	1		T1	1		T12	7		T8	1
valid_sources[0x30]	20760	1		T12	3		T14	5		T8	1
valid_sources[0x31]	22257	1		T1	5		T8	4		T4	4
valid_sources[0x32]	20873	1		T1	3		T2	5		T12	1
valid_sources[0x33]	20132	1		T12	2		T3	1		T8	2
valid_sources[0x34]	20233	1		T1	2		T12	5		T8	1
valid_sources[0x35]	21390	1		T1	2		T12	11		T14	15
valid_sources[0x36]	20500	1		T1	2		T12	5		T8	4
valid_sources[0x37]	21427	1		T12	3		T8	1		T4	2
valid_sources[0x38]	20290	1		T12	1		T8	3		T4	1
valid_sources[0x39]	21703	1		T1	1		T12	3		T3	1
valid_sources[0x3a]	20880	1		T1	2		T12	6		T3	3
valid_sources[0x3b]	23385	1		T12	4		T8	1		T4	1
valid_sources[0x3c]	21709	1		T1	1		T12	11		T8	3
valid_sources[0x3d]	22776	1		T1	2		T12	1		T8	3
valid_sources[0x3e]	20558	1		T8	3		T4	1		T45	3
valid_sources[0x3f]	21238	1		T1	1		T12	4		T3	1
valid_sources[0x40]	20103	1		T12	5		T3	1		T8	2
valid_sources[0x41]	19252	1		T14	17		T8	2		T5	1
valid_sources[0x42]	19847	1		T1	1		T2	3		T12	6
valid_sources[0x43]	20757	1		T1	4		T12	11		T4	1
valid_sources[0x44]	19753	1		T1	1		T12	1		T8	1
valid_sources[0x45]	19401	1		T12	13		T14	6		T11	10
valid_sources[0x46]	23829	1		T1	2		T12	11		T8	2
valid_sources[0x47]	21759	1		T1	2		T12	16		T8	3
valid_sources[0x48]	21416	1		T8	3		T4	1		T5	3
valid_sources[0x49]	19508	1		T12	2		T14	1		T3	3
valid_sources[0x4a]	21790	1		T12	4		T8	4		T4	4
valid_sources[0x4b]	20203	1		T1	2		T12	1		T8	2
valid_sources[0x4c]	21034	1		T1	1		T12	4		T8	3
valid_sources[0x4d]	21537	1		T1	1		T12	19		T4	1
valid_sources[0x4e]	21939	1		T1	2		T12	2		T14	13
valid_sources[0x4f]	21806	1		T1	4		T14	5		T8	1
valid_sources[0x50]	21488	1		T1	1		T12	4		T14	20
valid_sources[0x51]	21795	1		T8	1		T9	5		T11	1
valid_sources[0x52]	19155	1		T12	2		T14	3		T23	5
valid_sources[0x53]	21381	1		T1	3		T12	2		T8	6
valid_sources[0x54]	19674	1		T1	4		T12	1		T14	6
valid_sources[0x55]	22380	1		T1	3		T8	2		T5	1
valid_sources[0x56]	22038	1		T1	1		T12	2		T8	1
valid_sources[0x57]	20987	1		T1	1		T12	9		T8	3
valid_sources[0x58]	19865	1		T1	1		T8	3		T4	1
valid_sources[0x59]	20553	1		T1	3		T8	3		T4	1
valid_sources[0x5a]	22641	1		T1	3		T12	8		T8	2
valid_sources[0x5b]	19966	1		T1	1		T12	17		T3	4
valid_sources[0x5c]	20738	1		T12	1		T8	1		T9	2
valid_sources[0x5d]	20095	1		T1	2		T2	16		T8	1
valid_sources[0x5e]	20415	1		T12	2		T8	1		T4	1
valid_sources[0x5f]	21080	1		T1	5		T12	6		T3	1
valid_sources[0x60]	19663	1		T1	2		T8	3		T45	3
valid_sources[0x61]	20880	1		T1	2		T8	2		T4	1
valid_sources[0x62]	21729	1		T12	11		T3	1		T8	3
valid_sources[0x63]	21579	1		T1	4		T8	1		T4	1
valid_sources[0x64]	22822	1		T1	2		T8	5		T45	3
valid_sources[0x65]	20794	1		T1	1		T12	4		T4	1
valid_sources[0x66]	21072	1		T1	1		T8	2		T4	1
valid_sources[0x67]	19661	1		T12	2		T8	3		T4	1
valid_sources[0x68]	20436	1		T1	2		T12	3		T8	1
valid_sources[0x69]	20652	1		T4	1		T9	2		T24	3
valid_sources[0x6a]	20733	1		T1	4		T12	8		T8	2
valid_sources[0x6b]	19736	1		T1	5		T12	1		T8	2
valid_sources[0x6c]	21229	1		T1	6		T12	1		T14	6
valid_sources[0x6d]	19470	1		T12	5		T8	2		T9	2
valid_sources[0x6e]	19580	1		T12	3		T8	3		T4	1
valid_sources[0x6f]	21616	1		T7	7		T12	10		T8	1
valid_sources[0x70]	20258	1		T1	3		T12	6		T44	2
valid_sources[0x71]	18910	1		T1	1		T12	1		T3	1
valid_sources[0x72]	21180	1		T1	1		T2	1		T12	2
valid_sources[0x73]	20719	1		T12	7		T4	1		T9	3
valid_sources[0x74]	21771	1		T12	1		T8	3		T4	1
valid_sources[0x75]	20549	1		T1	1		T12	17		T8	1
valid_sources[0x76]	22009	1		T1	3		T12	2		T14	4
valid_sources[0x77]	20251	1		T12	2		T4	1		T9	8
valid_sources[0x78]	20584	1		T1	2		T8	4		T4	1
valid_sources[0x79]	20461	1		T12	5		T8	4		T6	3
valid_sources[0x7a]	19538	1		T12	1		T4	1		T9	1
valid_sources[0x7b]	21148	1		T1	2		T14	12		T4	1
valid_sources[0x7c]	20791	1		T1	3		T8	1		T4	1
valid_sources[0x7d]	22232	1		T12	1		T14	7		T8	3
valid_sources[0x7e]	20328	1		T12	2		T14	1		T4	1
valid_sources[0x7f]	20688	1		T12	1		T14	4		T8	3
valid_sources[0x80]	21633	1		T12	2		T8	1		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1246905

1

T1

58

T2

87

T7

11

values[0x0]

all_enables

biggest_size

1868737

1

T1

71

T2

68

T7

6

values[0x1]

all_enables

biggest_size

1866840

1

T1

82

T2

62

T7

2