Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	647140168	7139634	0	0
wdog_bark_thold_rd_A	647140168	115684	0	0
wdog_bite_thold_rd_A	647140168	100615	0	0
wdog_ctrl_rd_A	647140168	101703	0	0
wdog_regwen_rd_A	647140168	116728	0	0
wkup_ctrl_rd_A	647140168	102637	0	0
wkup_thold_rd_A	647140168	115771	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647140168	7139634	0	0
T1	806686	4	0	0
T2	202196	0	0	0
T3	52702	0	0	0
T4	44464	3	0	0
T7	46540	0	0	0
T8	399742	3	0	0
T9	0	7	0	0
T11	0	5	0	0
T12	280411	0	0	0
T13	17676	537	0	0
T14	25653	475	0	0
T15	7255	0	0	0
T23	0	635	0	0
T44	0	3	0	0
T48	0	436	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647140168	115684	0	0
T3	52702	0	0	0
T4	44464	0	0	0
T5	55618	13	0	0
T8	399742	0	0	0
T9	810479	0	0	0
T14	25653	17	0	0
T15	7255	0	0	0
T17	0	5102	0	0
T22	0	8766	0	0
T23	15359	0	0	0
T45	0	49	0	0
T46	0	2649	0	0
T47	25257	0	0	0
T49	28514	0	0	0
T75	0	12272	0	0
T76	0	2158	0	0
T77	0	6502	0	0
T78	0	23157	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647140168	100615	0	0
T3	52702	0	0	0
T4	44464	0	0	0
T5	55618	7	0	0
T8	399742	0	0	0
T9	810479	0	0	0
T14	25653	7	0	0
T15	7255	0	0	0
T17	0	4048	0	0
T22	0	7394	0	0
T23	15359	0	0	0
T45	0	85	0	0
T46	0	2321	0	0
T47	25257	0	0	0
T49	28514	0	0	0
T75	0	10322	0	0
T76	0	1906	0	0
T77	0	5722	0	0
T78	0	20202	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647140168	101703	0	0
T3	52702	0	0	0
T4	44464	0	0	0
T5	55618	44	0	0
T8	399742	0	0	0
T9	810479	0	0	0
T14	25653	12	0	0
T15	7255	0	0	0
T17	0	4512	0	0
T22	0	7354	0	0
T23	15359	0	0	0
T45	0	63	0	0
T46	0	1980	0	0
T47	25257	0	0	0
T49	28514	0	0	0
T75	0	11031	0	0
T76	0	1990	0	0
T77	0	5422	0	0
T78	0	19514	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647140168	116728	0	0
T3	52702	0	0	0
T4	44464	0	0	0
T5	55618	15	0	0
T8	399742	0	0	0
T9	810479	0	0	0
T14	25653	29	0	0
T15	7255	0	0	0
T17	0	4905	0	0
T22	0	9033	0	0
T23	15359	0	0	0
T45	0	77	0	0
T46	0	2291	0	0
T47	25257	0	0	0
T49	28514	0	0	0
T75	0	12642	0	0
T76	0	2406	0	0
T77	0	6329	0	0
T78	0	22366	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647140168	102637	0	0
T3	52702	0	0	0
T4	44464	0	0	0
T5	55618	3	0	0
T8	399742	0	0	0
T9	810479	0	0	0
T14	25653	62	0	0
T15	7255	0	0	0
T17	0	4431	0	0
T22	0	7140	0	0
T23	15359	0	0	0
T45	0	74	0	0
T46	0	2091	0	0
T47	25257	0	0	0
T49	28514	0	0	0
T75	0	10904	0	0
T76	0	1852	0	0
T77	0	5881	0	0
T78	0	20036	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	647140168	115771	0	0
T3	52702	0	0	0
T4	44464	0	0	0
T5	55618	40	0	0
T8	399742	0	0	0
T9	810479	0	0	0
T14	25653	33	0	0
T15	7255	0	0	0
T17	0	4684	0	0
T22	0	8572	0	0
T23	15359	0	0	0
T45	0	46	0	0
T46	0	2406	0	0
T47	25257	0	0	0
T49	28514	0	0	0
T75	0	12630	0	0
T76	0	2287	0	0
T77	0	6335	0	0
T78	0	22500	0	0