Unified Coverage Report :: Module

Module : aon_timer_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_core	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : aon_timer_core

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	38	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
ALWAYS	43	4	4	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	78	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
43	1	1
44	1	1
45	1	1
46	1	1
			MISSING_ELSE
51	1	1
55	1	1
56	1	1
59	1	1
66	1	1
70	1	1
71	1	1
74	1	1
76	1	1
78	1	1

Cond Coverage for Module : aon_timer_core

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       38
 EXPRESSION (wkup_incr ? 12'b0 : ((prescale_count_q + 12'b1)))
             ----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       59
 EXPRESSION (wkup_incr & (reg2hw_i.wkup_count.q >= reg2hw_i.wkup_thold.q))
             ----1----   ------------------------2-----------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T19
1	1	Covered	T16,T17,T18

 LINE       74
 EXPRESSION (wdog_incr & (reg2hw_i.wdog_count.q >= reg2hw_i.wdog_bark_thold.q))
             ----1----   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T20
1	1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (wdog_incr & (reg2hw_i.wdog_count.q >= reg2hw_i.wdog_bite_thold.q))
             ----1----   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T20
1	1	Covered	T17,T18,T22

Branch Coverage for Module : aon_timer_core

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	38	2	2	100.00
IF	43	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	38	(wkup_incr) ?

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	43	if ((!rst_aon_ni))
-2-:	45	if (prescale_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T17,T18
0	1	Covered	T16,T17,T18
0	0	Covered	T16,T17,T18