Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.45 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 5 136 96.45


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 27960 1 T13 539 T19 808 T20 11
bark[1] 692 1 T19 232 T21 12 T25 31
bark[2] 515 1 T13 32 T55 16 T82 16
bark[3] 727 1 T13 175 T23 12 T53 16
bark[4] 526 1 T24 16 T57 67 T83 26
bark[5] 480 1 T13 21 T24 27 T82 16
bark[6] 560 1 T84 17 T55 37 T61 22
bark[7] 1035 1 T54 227 T85 16 T86 12
bark[8] 835 1 T87 13 T55 16 T57 204
bark[9] 274 1 T25 22 T88 67 T89 169
bark[10] 267 1 T57 79 T90 70 T35 31
bark[11] 521 1 T24 16 T28 12 T85 17
bark[12] 175 1 T13 21 T56 4 T91 109
bark[13] 1147 1 T24 41 T54 367 T92 12
bark[14] 494 1 T53 26 T55 158 T56 26
bark[15] 482 1 T13 16 T53 17 T56 17
bark[16] 379 1 T22 52 T60 30 T84 33
bark[17] 390 1 T19 22 T24 16 T25 26
bark[18] 753 1 T13 16 T93 17 T94 12
bark[19] 560 1 T13 118 T27 16 T54 16
bark[20] 208 1 T57 21 T61 16 T95 63
bark[21] 1026 1 T22 46 T60 17 T57 32
bark[22] 519 1 T55 185 T96 61 T97 50
bark[23] 1330 1 T13 252 T22 17 T27 37
bark[24] 319 1 T60 17 T53 153 T98 17
bark[25] 456 1 T84 16 T96 75 T91 53
bark[26] 546 1 T13 154 T27 16 T99 31
bark[27] 541 1 T100 12 T85 16 T101 53
bark[28] 491 1 T24 16 T56 22 T57 89
bark[29] 672 1 T22 17 T53 22 T102 16
bark[30] 671 1 T22 16 T53 69 T82 16
bark[31] 363 1 T13 17 T19 148 T84 34
bark_0 3784 1 T14 5 T15 6 T16 10


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 27841 1 T13 535 T19 802 T20 10
bite[1] 356 1 T24 27 T61 72 T103 11
bite[2] 339 1 T21 11 T24 16 T82 16
bite[3] 592 1 T102 17 T90 12 T35 11
bite[4] 390 1 T19 231 T84 17 T54 16
bite[5] 770 1 T28 11 T55 157 T104 254
bite[6] 777 1 T22 16 T54 366 T61 16
bite[7] 742 1 T13 174 T53 25 T96 136
bite[8] 919 1 T19 147 T25 22 T54 226
bite[9] 950 1 T60 47 T55 184 T102 21
bite[10] 721 1 T13 16 T53 17 T56 22
bite[11] 251 1 T13 20 T104 23 T105 17
bite[12] 458 1 T24 16 T84 17 T56 17
bite[13] 488 1 T19 22 T27 36 T55 16
bite[14] 486 1 T106 16 T93 16 T62 86
bite[15] 592 1 T25 31 T84 16 T55 16
bite[16] 414 1 T13 17 T107 11 T108 11
bite[17] 636 1 T13 20 T24 32 T97 49
bite[18] 910 1 T56 227 T57 203 T93 16
bite[19] 440 1 T22 63 T55 59 T102 17
bite[20] 837 1 T13 251 T101 53 T109 16
bite[21] 949 1 T22 17 T87 12 T57 269
bite[22] 519 1 T100 11 T55 41 T61 16
bite[23] 462 1 T22 52 T57 20 T85 33
bite[24] 551 1 T23 11 T84 17 T61 212
bite[25] 134 1 T53 16 T106 17 T110 16
bite[26] 430 1 T25 26 T60 17 T57 93
bite[27] 881 1 T13 270 T27 16 T84 17
bite[28] 284 1 T13 16 T24 41 T56 3
bite[29] 208 1 T84 16 T111 12 T112 36
bite[30] 504 1 T53 22 T93 16 T88 26
bite[31] 549 1 T13 32 T53 152 T92 11
bite_0 4318 1 T14 5 T15 6 T16 10


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 49698 1 T14 5 T15 6 T16 10


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1112 1 T19 37 T27 15 T55 72
prescale[1] 1001 1 T19 15 T22 18 T56 61
prescale[2] 596 1 T113 8 T102 18 T82 31
prescale[3] 945 1 T84 18 T55 8 T99 8
prescale[4] 867 1 T13 15 T27 41 T55 43
prescale[5] 571 1 T83 20 T82 46 T61 80
prescale[6] 1213 1 T19 82 T55 63 T56 15
prescale[7] 836 1 T13 42 T19 21 T27 83
prescale[8] 796 1 T13 8 T19 70 T22 15
prescale[9] 885 1 T13 122 T19 15 T27 20
prescale[10] 875 1 T19 123 T27 29 T24 15
prescale[11] 824 1 T13 49 T19 15 T27 40
prescale[12] 940 1 T19 176 T55 59 T56 75
prescale[13] 795 1 T13 2 T27 139 T57 32
prescale[14] 948 1 T27 2 T54 116 T56 60
prescale[15] 668 1 T13 4 T19 29 T22 18
prescale[16] 749 1 T25 33 T54 53 T56 15
prescale[17] 573 1 T19 8 T56 17 T106 98
prescale[18] 618 1 T13 94 T19 60 T27 46
prescale[19] 843 1 T55 84 T57 2 T114 15
prescale[20] 989 1 T19 39 T27 99 T53 10
prescale[21] 558 1 T13 148 T19 44 T60 15
prescale[22] 1074 1 T13 167 T19 121 T27 92
prescale[23] 544 1 T27 123 T24 8 T60 18
prescale[24] 1050 1 T24 41 T54 8 T55 2
prescale[25] 644 1 T13 2 T19 15 T54 2
prescale[26] 721 1 T27 2 T60 15 T84 15
prescale[27] 855 1 T13 15 T19 2 T20 8
prescale[28] 743 1 T22 49 T27 45 T84 51
prescale[29] 998 1 T19 2 T27 80 T24 35
prescale[30] 776 1 T27 45 T54 153 T56 23
prescale[31] 610 1 T13 44 T19 87 T53 31
prescale_0 23481 1 T14 5 T15 6 T16 10


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36396 1 T14 5 T15 6 T16 10
auto[1] 13302 1 T13 283 T19 151 T20 9


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 49698 1 T14 5 T15 6 T16 10


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 29799 1 T13 901 T19 885 T20 12
wkup[1] 557 1 T27 16 T84 16 T54 16
wkup[2] 544 1 T13 16 T19 16 T55 28
wkup[3] 585 1 T19 38 T22 16 T27 16
wkup[4] 679 1 T13 16 T19 16 T27 32
wkup[5] 582 1 T13 16 T22 17 T27 32
wkup[6] 428 1 T13 16 T21 13 T27 16
wkup[7] 578 1 T13 32 T19 16 T22 17
wkup[8] 707 1 T13 30 T22 16 T84 17
wkup[9] 406 1 T53 16 T54 31 T55 42
wkup[10] 334 1 T27 13 T25 26 T84 17
wkup[11] 413 1 T22 16 T27 16 T54 25
wkup[12] 708 1 T13 32 T19 16 T24 16
wkup[13] 551 1 T13 33 T19 37 T27 35
wkup[14] 543 1 T13 16 T19 45 T27 13
wkup[15] 409 1 T13 32 T19 17 T55 16
wkup[16] 406 1 T23 13 T27 16 T106 17
wkup[17] 543 1 T13 17 T28 13 T60 16
wkup[18] 577 1 T13 32 T19 16 T27 32
wkup[19] 491 1 T13 21 T27 16 T24 16
wkup[20] 393 1 T13 16 T27 16 T57 16
wkup[21] 596 1 T13 32 T27 16 T54 16
wkup[22] 640 1 T13 26 T19 16 T22 16
wkup[23] 536 1 T87 14 T53 23 T54 17
wkup[24] 752 1 T13 38 T27 16 T55 23
wkup[25] 555 1 T19 16 T27 16 T57 26
wkup[26] 571 1 T19 67 T27 39 T55 49
wkup[27] 462 1 T27 32 T84 17 T54 22
wkup[28] 478 1 T22 16 T27 48 T24 27
wkup[29] 552 1 T13 49 T53 17 T55 16
wkup[30] 520 1 T27 16 T60 17 T54 16
wkup[31] 606 1 T19 17 T27 26 T53 16
wkup_0 3197 1 T14 5 T15 6 T16 10

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