ASSERT | PROPERTIES | SEQUENCES | |
Total | 377 | 0 | 10 |
Category 0 | 377 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 377 | 0 | 10 |
Severity 0 | 377 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 377 | 100.00 |
Uncovered | 0 | 0.00 |
Success | 377 | 100.00 |
Failure | 0 | 0.00 |
Incomplete | 4 | 1.06 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_lc_sync_escalate_en.gen_flops.OutputDelay_A | 0 | 0 | 3833838 | 3770209 | 0 | 745 | |
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3883295 | 567 | 0 | 431 | |
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3883295 | 1462 | 0 | 429 | |
tb.dut.u_reg.u_wkup_count_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3883295 | 3091 | 0 | 429 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 820728677 | 154204 | 154204 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 820728677 | 611 | 611 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 820728677 | 1477 | 1477 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 820728677 | 920 | 920 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 820728677 | 1350 | 1350 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 820728677 | 721 | 721 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 820728677 | 410 | 410 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 820728677 | 715 | 715 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 820728677 | 1802 | 1802 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 820728677 | 13980 | 13980 | 361 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 820728677 | 154204 | 154204 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 820728677 | 611 | 611 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 820728677 | 1477 | 1477 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 820728677 | 920 | 920 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 820728677 | 1350 | 1350 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 820728677 | 721 | 721 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 820728677 | 410 | 410 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 820728677 | 715 | 715 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 820728677 | 1802 | 1802 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 820728677 | 13980 | 13980 | 361 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |