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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.56 99.82 95.31 100.00 99.35 100.00 96.90


Total test records in report: 429
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T271 /workspace/coverage/default/4.aon_timer_stress_all.1855961108 Jan 21 09:02:04 PM PST 24 Jan 21 09:10:25 PM PST 24 318386093120 ps
T272 /workspace/coverage/default/21.aon_timer_stress_all.645356600 Jan 21 09:38:08 PM PST 24 Jan 21 09:41:59 PM PST 24 327973188735 ps
T273 /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3743488621 Jan 21 09:04:29 PM PST 24 Jan 21 09:14:35 PM PST 24 76849851509 ps
T274 /workspace/coverage/default/43.aon_timer_smoke.121408228 Jan 21 09:04:22 PM PST 24 Jan 21 09:04:30 PM PST 24 426613527 ps
T275 /workspace/coverage/default/15.aon_timer_smoke.2308936096 Jan 21 09:02:37 PM PST 24 Jan 21 09:02:46 PM PST 24 409341296 ps
T276 /workspace/coverage/default/37.aon_timer_jump.3479979954 Jan 21 09:03:24 PM PST 24 Jan 21 09:03:42 PM PST 24 346473552 ps
T277 /workspace/coverage/default/18.aon_timer_jump.2514587998 Jan 21 09:02:49 PM PST 24 Jan 21 09:02:54 PM PST 24 565525806 ps
T278 /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.516432000 Jan 21 09:01:55 PM PST 24 Jan 21 09:10:46 PM PST 24 166712124808 ps
T279 /workspace/coverage/default/21.aon_timer_jump.4117750940 Jan 21 09:52:21 PM PST 24 Jan 21 09:52:25 PM PST 24 524419530 ps
T280 /workspace/coverage/default/0.aon_timer_jump.2748357529 Jan 21 09:01:50 PM PST 24 Jan 21 09:02:07 PM PST 24 387273696 ps
T281 /workspace/coverage/default/14.aon_timer_stress_all.809753400 Jan 21 09:02:27 PM PST 24 Jan 21 09:04:10 PM PST 24 355395613788 ps
T32 /workspace/coverage/default/1.aon_timer_sec_cm.2792114227 Jan 21 09:02:03 PM PST 24 Jan 21 09:02:20 PM PST 24 4586781011 ps
T282 /workspace/coverage/default/46.aon_timer_prescaler.2144953448 Jan 21 09:04:31 PM PST 24 Jan 21 09:04:51 PM PST 24 8239934624 ps
T283 /workspace/coverage/default/7.aon_timer_stress_all.2236206463 Jan 21 09:02:14 PM PST 24 Jan 21 09:03:19 PM PST 24 138377191711 ps
T284 /workspace/coverage/default/32.aon_timer_smoke.3960550289 Jan 21 09:03:05 PM PST 24 Jan 21 09:03:10 PM PST 24 377779404 ps
T285 /workspace/coverage/default/5.aon_timer_prescaler.567483176 Jan 21 09:02:01 PM PST 24 Jan 21 09:02:22 PM PST 24 2961681430 ps
T33 /workspace/coverage/default/2.aon_timer_sec_cm.1434971301 Jan 21 09:22:59 PM PST 24 Jan 21 09:23:02 PM PST 24 7672581351 ps
T286 /workspace/coverage/default/10.aon_timer_stress_all.1886913976 Jan 21 09:02:27 PM PST 24 Jan 21 09:03:53 PM PST 24 427168147970 ps
T287 /workspace/coverage/default/43.aon_timer_stress_all.4268303193 Jan 21 09:04:29 PM PST 24 Jan 21 09:04:46 PM PST 24 24115088424 ps
T288 /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2603606760 Jan 21 10:48:02 PM PST 24 Jan 21 10:54:57 PM PST 24 50398083248 ps
T289 /workspace/coverage/default/26.aon_timer_stress_all.924996347 Jan 21 09:03:03 PM PST 24 Jan 21 09:05:59 PM PST 24 126388582466 ps
T290 /workspace/coverage/default/17.aon_timer_smoke.4010825481 Jan 21 09:02:32 PM PST 24 Jan 21 09:02:43 PM PST 24 573002533 ps
T291 /workspace/coverage/default/18.aon_timer_prescaler.3636561369 Jan 21 09:02:44 PM PST 24 Jan 21 09:03:03 PM PST 24 8972109260 ps
T292 /workspace/coverage/default/2.aon_timer_prescaler.2973794264 Jan 21 09:02:08 PM PST 24 Jan 21 09:02:42 PM PST 24 23449983468 ps
T293 /workspace/coverage/default/9.aon_timer_jump.2841655846 Jan 21 09:02:15 PM PST 24 Jan 21 09:02:31 PM PST 24 391719043 ps
T294 /workspace/coverage/default/18.aon_timer_smoke.2150600330 Jan 21 09:02:45 PM PST 24 Jan 21 09:02:50 PM PST 24 610066269 ps
T295 /workspace/coverage/default/18.aon_timer_stress_all.17877830 Jan 21 09:02:50 PM PST 24 Jan 21 09:08:35 PM PST 24 258106796374 ps
T296 /workspace/coverage/default/13.aon_timer_jump.3910505329 Jan 21 09:02:26 PM PST 24 Jan 21 09:02:38 PM PST 24 344623048 ps
T297 /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3557602918 Jan 21 09:03:00 PM PST 24 Jan 21 09:09:13 PM PST 24 128783583413 ps
T298 /workspace/coverage/default/6.aon_timer_jump.3480278026 Jan 21 10:52:50 PM PST 24 Jan 21 10:52:52 PM PST 24 581251726 ps
T299 /workspace/coverage/default/15.aon_timer_prescaler.2657973936 Jan 21 09:02:35 PM PST 24 Jan 21 09:03:59 PM PST 24 51265197253 ps
T300 /workspace/coverage/default/49.aon_timer_smoke.3808458136 Jan 21 09:04:35 PM PST 24 Jan 21 09:04:40 PM PST 24 399686953 ps
T301 /workspace/coverage/default/8.aon_timer_prescaler.838759881 Jan 21 09:02:15 PM PST 24 Jan 21 09:02:50 PM PST 24 54734445505 ps
T74 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2115136908 Jan 21 08:58:49 PM PST 24 Jan 21 08:59:17 PM PST 24 356054131 ps
T302 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2766494191 Jan 21 09:00:06 PM PST 24 Jan 21 09:00:34 PM PST 24 481779711 ps
T75 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.374250612 Jan 21 08:59:36 PM PST 24 Jan 21 08:59:57 PM PST 24 1166810952 ps
T303 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4293540982 Jan 21 09:00:08 PM PST 24 Jan 21 09:00:37 PM PST 24 1229033932 ps
T304 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2432264028 Jan 21 08:59:19 PM PST 24 Jan 21 08:59:45 PM PST 24 597389860 ps
T305 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3508049603 Jan 21 08:58:48 PM PST 24 Jan 21 08:59:16 PM PST 24 484359463 ps
T64 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.147712213 Jan 21 08:59:19 PM PST 24 Jan 21 08:59:43 PM PST 24 476708811 ps
T65 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1899151103 Jan 21 08:59:07 PM PST 24 Jan 21 08:59:41 PM PST 24 2032841848 ps
T306 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3894759672 Jan 21 08:59:16 PM PST 24 Jan 21 08:59:41 PM PST 24 504452711 ps
T66 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2292663639 Jan 21 08:58:56 PM PST 24 Jan 21 08:59:22 PM PST 24 793614010 ps
T307 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.4212436231 Jan 21 09:41:28 PM PST 24 Jan 21 09:41:30 PM PST 24 352813641 ps
T308 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1306867447 Jan 21 08:59:35 PM PST 24 Jan 21 08:59:57 PM PST 24 4945762112 ps
T309 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.825825942 Jan 21 08:59:19 PM PST 24 Jan 21 08:59:43 PM PST 24 310907209 ps
T310 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2093875064 Jan 21 09:00:18 PM PST 24 Jan 21 09:00:46 PM PST 24 311848345 ps
T67 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1093635427 Jan 21 09:00:05 PM PST 24 Jan 21 09:00:33 PM PST 24 490568152 ps
T76 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3968658080 Jan 21 09:00:08 PM PST 24 Jan 21 09:00:37 PM PST 24 1689734888 ps
T311 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.535736624 Jan 21 08:59:34 PM PST 24 Jan 21 08:59:56 PM PST 24 395472205 ps
T312 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.893156802 Jan 21 09:00:23 PM PST 24 Jan 21 09:00:51 PM PST 24 350760215 ps
T313 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3805820288 Jan 21 09:00:24 PM PST 24 Jan 21 09:00:52 PM PST 24 417041742 ps
T77 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3992797442 Jan 21 08:59:22 PM PST 24 Jan 21 08:59:46 PM PST 24 917586274 ps
T314 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1498763074 Jan 21 09:20:34 PM PST 24 Jan 21 09:20:36 PM PST 24 280094679 ps
T315 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1608458242 Jan 21 09:00:09 PM PST 24 Jan 21 09:00:38 PM PST 24 304505166 ps
T316 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.716864352 Jan 21 09:00:18 PM PST 24 Jan 21 09:00:47 PM PST 24 403838484 ps
T68 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.476246162 Jan 21 08:59:12 PM PST 24 Jan 21 08:59:38 PM PST 24 449693614 ps
T317 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.853497719 Jan 21 08:59:21 PM PST 24 Jan 21 08:59:46 PM PST 24 310302937 ps
T69 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.135740278 Jan 21 08:59:29 PM PST 24 Jan 21 08:59:52 PM PST 24 533905944 ps
T70 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1713221744 Jan 21 08:59:21 PM PST 24 Jan 21 08:59:45 PM PST 24 520803502 ps
T318 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.35498783 Jan 21 08:58:50 PM PST 24 Jan 21 08:59:17 PM PST 24 301718308 ps
T71 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.333065954 Jan 21 08:59:18 PM PST 24 Jan 21 08:59:42 PM PST 24 520223481 ps
T81 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.278670082 Jan 21 08:59:29 PM PST 24 Jan 21 08:59:53 PM PST 24 4367084750 ps
T319 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3403677719 Jan 21 08:59:35 PM PST 24 Jan 21 08:59:56 PM PST 24 408353726 ps
T320 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2930318009 Jan 21 08:59:53 PM PST 24 Jan 21 09:00:18 PM PST 24 1252992416 ps
T321 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.4127842747 Jan 21 09:00:15 PM PST 24 Jan 21 09:00:44 PM PST 24 305093949 ps
T322 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2556597152 Jan 21 08:59:44 PM PST 24 Jan 21 09:00:03 PM PST 24 346925060 ps
T72 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1076941311 Jan 21 08:59:51 PM PST 24 Jan 21 09:00:14 PM PST 24 402609311 ps
T323 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.428370859 Jan 21 09:00:01 PM PST 24 Jan 21 09:00:30 PM PST 24 1054464297 ps
T324 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1864567743 Jan 21 09:00:15 PM PST 24 Jan 21 09:00:44 PM PST 24 408660774 ps
T325 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1441805208 Jan 21 08:59:09 PM PST 24 Jan 21 08:59:35 PM PST 24 1278434779 ps
T326 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.384131783 Jan 21 08:59:24 PM PST 24 Jan 21 08:59:48 PM PST 24 400249167 ps
T327 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3448240969 Jan 21 09:00:24 PM PST 24 Jan 21 09:00:52 PM PST 24 338865606 ps
T328 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1430785787 Jan 21 08:58:58 PM PST 24 Jan 21 08:59:24 PM PST 24 519702458 ps
T329 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.956844160 Jan 21 09:00:08 PM PST 24 Jan 21 09:00:37 PM PST 24 493952992 ps
T330 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1182360448 Jan 21 08:59:24 PM PST 24 Jan 21 08:59:48 PM PST 24 4402031140 ps
T73 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.879279487 Jan 21 09:00:07 PM PST 24 Jan 21 09:00:35 PM PST 24 525177195 ps
T331 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3263487402 Jan 21 09:00:22 PM PST 24 Jan 21 09:00:50 PM PST 24 443935761 ps
T332 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.165227513 Jan 21 09:00:06 PM PST 24 Jan 21 09:00:36 PM PST 24 541877380 ps
T78 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1001165377 Jan 21 08:58:50 PM PST 24 Jan 21 08:59:18 PM PST 24 9348210486 ps
T333 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2553281795 Jan 21 08:59:05 PM PST 24 Jan 21 08:59:34 PM PST 24 428046862 ps
T334 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.228054465 Jan 21 08:59:53 PM PST 24 Jan 21 09:00:16 PM PST 24 411388321 ps
T335 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3696201973 Jan 21 10:00:02 PM PST 24 Jan 21 10:00:09 PM PST 24 2186446355 ps
T336 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.778890910 Jan 21 10:47:36 PM PST 24 Jan 21 10:47:39 PM PST 24 363559303 ps
T337 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1624724918 Jan 21 08:59:43 PM PST 24 Jan 21 09:00:03 PM PST 24 373959997 ps
T338 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3170443390 Jan 21 08:59:19 PM PST 24 Jan 21 08:59:44 PM PST 24 503950358 ps
T339 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3381685574 Jan 21 09:00:08 PM PST 24 Jan 21 09:00:36 PM PST 24 538187351 ps
T340 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2792478622 Jan 21 09:00:01 PM PST 24 Jan 21 09:00:28 PM PST 24 385217158 ps
T341 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3560617798 Jan 21 09:00:29 PM PST 24 Jan 21 09:00:58 PM PST 24 297852344 ps
T342 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3683070488 Jan 21 08:59:39 PM PST 24 Jan 21 09:00:02 PM PST 24 2442857681 ps
T343 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2716927045 Jan 21 08:59:35 PM PST 24 Jan 21 08:59:55 PM PST 24 462501921 ps
T79 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3721520886 Jan 21 09:00:06 PM PST 24 Jan 21 09:00:38 PM PST 24 4145856867 ps
T344 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2186671568 Jan 21 09:17:38 PM PST 24 Jan 21 09:17:43 PM PST 24 876284062 ps
T345 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2944492794 Jan 21 08:59:50 PM PST 24 Jan 21 09:00:12 PM PST 24 522328578 ps
T80 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.723135598 Jan 21 09:00:02 PM PST 24 Jan 21 09:00:35 PM PST 24 3921688899 ps
T346 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.563155593 Jan 21 09:32:17 PM PST 24 Jan 21 09:32:37 PM PST 24 331165149 ps
T347 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2589200203 Jan 21 08:59:10 PM PST 24 Jan 21 08:59:37 PM PST 24 437586857 ps
T348 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1150805627 Jan 21 08:59:05 PM PST 24 Jan 21 08:59:32 PM PST 24 449385468 ps
T349 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3743054917 Jan 21 09:00:00 PM PST 24 Jan 21 09:00:27 PM PST 24 403623014 ps
T350 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.150825967 Jan 21 08:58:54 PM PST 24 Jan 21 08:59:20 PM PST 24 305943977 ps
T351 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2704922828 Jan 21 09:45:33 PM PST 24 Jan 21 09:45:36 PM PST 24 1246203506 ps
T352 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1186601030 Jan 21 08:59:38 PM PST 24 Jan 21 09:00:03 PM PST 24 8327965426 ps
T353 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.882359399 Jan 21 08:59:09 PM PST 24 Jan 21 08:59:36 PM PST 24 452177316 ps
T354 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.599884331 Jan 21 08:59:36 PM PST 24 Jan 21 09:00:02 PM PST 24 4248200358 ps
T355 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2622679103 Jan 21 08:59:24 PM PST 24 Jan 21 08:59:48 PM PST 24 387925784 ps
T356 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3477730829 Jan 21 09:00:22 PM PST 24 Jan 21 09:00:50 PM PST 24 368407101 ps
T357 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1904730765 Jan 21 08:59:54 PM PST 24 Jan 21 09:00:22 PM PST 24 1689441719 ps
T358 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3486116871 Jan 21 08:59:35 PM PST 24 Jan 21 08:59:56 PM PST 24 324420949 ps
T359 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3666504815 Jan 21 08:59:23 PM PST 24 Jan 21 08:59:46 PM PST 24 358150445 ps
T360 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.51862951 Jan 21 08:59:19 PM PST 24 Jan 21 08:59:43 PM PST 24 401976316 ps
T361 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1161994677 Jan 21 08:59:18 PM PST 24 Jan 21 08:59:44 PM PST 24 1052094759 ps
T362 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3479849724 Jan 21 09:00:08 PM PST 24 Jan 21 09:00:36 PM PST 24 331175712 ps
T363 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1485693276 Jan 21 08:59:28 PM PST 24 Jan 21 08:59:50 PM PST 24 523158512 ps
T364 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2452060077 Jan 21 08:59:49 PM PST 24 Jan 21 09:00:10 PM PST 24 590241847 ps
T365 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.54244699 Jan 21 11:05:56 PM PST 24 Jan 21 11:06:00 PM PST 24 546944341 ps
T366 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3876704856 Jan 21 09:00:25 PM PST 24 Jan 21 09:00:53 PM PST 24 310161113 ps
T367 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4044604177 Jan 21 09:00:07 PM PST 24 Jan 21 09:00:36 PM PST 24 507358469 ps
T368 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4241866859 Jan 21 08:58:48 PM PST 24 Jan 21 08:59:16 PM PST 24 309422067 ps
T369 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1375253965 Jan 21 08:59:37 PM PST 24 Jan 21 08:59:59 PM PST 24 572605933 ps
T370 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3677808392 Jan 21 09:00:09 PM PST 24 Jan 21 09:00:39 PM PST 24 566206627 ps
T371 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2766047046 Jan 21 08:59:38 PM PST 24 Jan 21 08:59:59 PM PST 24 350262085 ps
T372 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.4060456341 Jan 21 09:00:02 PM PST 24 Jan 21 09:00:31 PM PST 24 1297914113 ps
T373 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3928248301 Jan 21 08:59:19 PM PST 24 Jan 21 08:59:49 PM PST 24 4600285316 ps
T374 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2668221160 Jan 21 09:00:01 PM PST 24 Jan 21 09:00:28 PM PST 24 1212619530 ps
T375 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1965481812 Jan 21 08:59:19 PM PST 24 Jan 21 08:59:44 PM PST 24 4341769135 ps
T376 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3679676340 Jan 21 08:58:53 PM PST 24 Jan 21 08:59:21 PM PST 24 1142199380 ps
T377 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2581649532 Jan 21 08:59:04 PM PST 24 Jan 21 08:59:30 PM PST 24 535889115 ps
T378 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3593726081 Jan 21 09:00:08 PM PST 24 Jan 21 09:00:37 PM PST 24 401955541 ps
T379 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1775449782 Jan 21 08:58:46 PM PST 24 Jan 21 08:59:15 PM PST 24 281803873 ps
T380 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.4053464631 Jan 21 08:59:50 PM PST 24 Jan 21 09:00:12 PM PST 24 440345555 ps
T381 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.737270754 Jan 21 08:59:39 PM PST 24 Jan 21 09:00:00 PM PST 24 415499170 ps
T382 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.536878226 Jan 21 08:59:15 PM PST 24 Jan 21 08:59:40 PM PST 24 400996445 ps
T383 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.945174496 Jan 21 09:00:26 PM PST 24 Jan 21 09:00:54 PM PST 24 363115214 ps
T384 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1623927068 Jan 21 08:59:13 PM PST 24 Jan 21 08:59:38 PM PST 24 428163948 ps
T385 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.70630945 Jan 21 08:59:18 PM PST 24 Jan 21 08:59:43 PM PST 24 442912296 ps
T386 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.674336363 Jan 21 08:59:20 PM PST 24 Jan 21 08:59:48 PM PST 24 4564231933 ps
T387 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1214742727 Jan 21 08:59:16 PM PST 24 Jan 21 08:59:40 PM PST 24 532510522 ps
T388 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.889137057 Jan 21 08:59:07 PM PST 24 Jan 21 08:59:34 PM PST 24 540547242 ps
T389 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3818727655 Jan 21 08:59:44 PM PST 24 Jan 21 09:00:04 PM PST 24 1208172753 ps
T390 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1196044979 Jan 21 09:00:17 PM PST 24 Jan 21 09:00:46 PM PST 24 516978867 ps
T391 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2038645190 Jan 21 08:58:57 PM PST 24 Jan 21 08:59:24 PM PST 24 391164587 ps
T392 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1068772687 Jan 21 09:00:25 PM PST 24 Jan 21 09:00:53 PM PST 24 412022496 ps
T393 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.283359458 Jan 21 08:58:59 PM PST 24 Jan 21 08:59:25 PM PST 24 519976150 ps
T394 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.438658660 Jan 21 08:59:21 PM PST 24 Jan 21 08:59:45 PM PST 24 432969846 ps
T395 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2997855777 Jan 21 08:59:50 PM PST 24 Jan 21 09:00:15 PM PST 24 3826340823 ps
T396 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1990593414 Jan 21 08:58:48 PM PST 24 Jan 21 08:59:17 PM PST 24 619813183 ps
T397 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2499468922 Jan 21 09:13:29 PM PST 24 Jan 21 09:13:32 PM PST 24 416861136 ps
T398 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3281354875 Jan 21 08:59:07 PM PST 24 Jan 21 08:59:43 PM PST 24 11387240432 ps
T399 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1040774 Jan 21 08:59:22 PM PST 24 Jan 21 08:59:47 PM PST 24 321893058 ps
T400 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1715086213 Jan 21 08:59:01 PM PST 24 Jan 21 08:59:31 PM PST 24 7674289106 ps
T401 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2651885314 Jan 21 09:00:07 PM PST 24 Jan 21 09:00:39 PM PST 24 8403465634 ps
T402 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.781737890 Jan 21 08:59:35 PM PST 24 Jan 21 08:59:57 PM PST 24 736647843 ps
T403 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.514071192 Jan 21 08:59:15 PM PST 24 Jan 21 08:59:44 PM PST 24 2545641461 ps
T404 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2433621297 Jan 21 10:12:18 PM PST 24 Jan 21 10:12:21 PM PST 24 493518572 ps
T405 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1817302382 Jan 21 09:00:06 PM PST 24 Jan 21 09:00:36 PM PST 24 8890910341 ps
T406 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1029012959 Jan 21 09:00:18 PM PST 24 Jan 21 09:00:46 PM PST 24 314091296 ps
T407 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.51641422 Jan 21 09:00:15 PM PST 24 Jan 21 09:00:45 PM PST 24 358544965 ps
T408 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.109487675 Jan 21 08:59:19 PM PST 24 Jan 21 08:59:45 PM PST 24 996727439 ps
T409 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3412954709 Jan 21 09:00:26 PM PST 24 Jan 21 09:00:55 PM PST 24 282397006 ps
T410 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2638021555 Jan 21 09:00:09 PM PST 24 Jan 21 09:00:37 PM PST 24 510246620 ps
T411 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2008809648 Jan 21 08:58:44 PM PST 24 Jan 21 08:59:15 PM PST 24 543689868 ps
T412 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3321398388 Jan 21 08:59:52 PM PST 24 Jan 21 09:00:26 PM PST 24 8120661270 ps
T413 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1668377535 Jan 21 08:59:24 PM PST 24 Jan 21 08:59:50 PM PST 24 8240973690 ps
T414 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.381407088 Jan 21 08:59:51 PM PST 24 Jan 21 09:00:14 PM PST 24 352664808 ps
T415 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4123794506 Jan 21 08:59:59 PM PST 24 Jan 21 09:00:26 PM PST 24 585278073 ps
T416 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3533391335 Jan 21 09:07:12 PM PST 24 Jan 21 09:07:27 PM PST 24 324176344 ps
T417 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1915938765 Jan 21 08:59:19 PM PST 24 Jan 21 08:59:44 PM PST 24 1940741944 ps
T418 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.319941379 Jan 21 09:00:09 PM PST 24 Jan 21 09:00:38 PM PST 24 587335204 ps
T419 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.82430523 Jan 21 08:59:18 PM PST 24 Jan 21 08:59:44 PM PST 24 446681604 ps
T420 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1225737185 Jan 21 09:00:07 PM PST 24 Jan 21 09:00:37 PM PST 24 670274421 ps
T421 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1171267893 Jan 21 08:58:58 PM PST 24 Jan 21 08:59:26 PM PST 24 296804975 ps
T422 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4263086254 Jan 21 08:59:08 PM PST 24 Jan 21 08:59:34 PM PST 24 428752341 ps
T423 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.499847050 Jan 21 09:00:19 PM PST 24 Jan 21 09:00:48 PM PST 24 296285130 ps
T424 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2992049722 Jan 21 09:00:02 PM PST 24 Jan 21 09:00:29 PM PST 24 562373483 ps
T425 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.462231973 Jan 21 09:00:09 PM PST 24 Jan 21 09:00:38 PM PST 24 545521296 ps
T426 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1544039640 Jan 21 08:59:26 PM PST 24 Jan 21 08:59:49 PM PST 24 511728869 ps
T427 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1198466030 Jan 21 08:59:59 PM PST 24 Jan 21 09:00:27 PM PST 24 509945150 ps
T428 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2658303041 Jan 21 09:00:28 PM PST 24 Jan 21 09:00:55 PM PST 24 427092971 ps
T429 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3102279421 Jan 21 08:59:24 PM PST 24 Jan 21 08:59:48 PM PST 24 440395945 ps

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2712633638
Short name T3
Test name
Test status
Simulation time 8540922572 ps
CPU time 4.65 seconds
Started Jan 21 08:58:48 PM PST 24
Finished Jan 21 08:59:20 PM PST 24
Peak memory 197428 kb
Host smart-f64d0b00-3329-41f2-b26c-3e7908d66070
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712633638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2712633638
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1363192807
Short name T13
Test name
Test status
Simulation time 176839918593 ps
CPU time 353.52 seconds
Started Jan 21 09:02:27 PM PST 24
Finished Jan 21 09:08:31 PM PST 24
Peak memory 197908 kb
Host smart-c282fd28-a57f-47df-9443-add76040d292
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363192807 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1363192807
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2388860313
Short name T57
Test name
Test status
Simulation time 79428811979 ps
CPU time 259.61 seconds
Started Jan 21 09:03:02 PM PST 24
Finished Jan 21 09:07:26 PM PST 24
Peak memory 197984 kb
Host smart-1ff14411-8edf-4616-991b-fa9ff5c0e651
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388860313 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2388860313
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2071051660
Short name T82
Test name
Test status
Simulation time 59343443541 ps
CPU time 457.35 seconds
Started Jan 21 09:51:33 PM PST 24
Finished Jan 21 09:59:17 PM PST 24
Peak memory 198016 kb
Host smart-dcf41b9e-7abc-4f49-8de5-e5d25c7a7df1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071051660 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2071051660
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.4288408811
Short name T61
Test name
Test status
Simulation time 39391268354 ps
CPU time 435.37 seconds
Started Jan 21 09:04:32 PM PST 24
Finished Jan 21 09:11:53 PM PST 24
Peak memory 197948 kb
Host smart-2e0d1b6b-9f65-4dc3-a51a-783587d4fb06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288408811 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.4288408811
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.933612426
Short name T6
Test name
Test status
Simulation time 7891126597 ps
CPU time 17.97 seconds
Started Jan 21 08:59:12 PM PST 24
Finished Jan 21 08:59:55 PM PST 24
Peak memory 191992 kb
Host smart-1c08c96f-c265-442d-a620-6ac61ef4158d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933612426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.933612426
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.4290226985
Short name T203
Test name
Test status
Simulation time 156366924429 ps
CPU time 659.61 seconds
Started Jan 21 09:01:58 PM PST 24
Finished Jan 21 09:13:14 PM PST 24
Peak memory 198896 kb
Host smart-5b27b69d-2448-4aa6-8fb3-ae7aca46e24d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290226985 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.4290226985
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1338590974
Short name T56
Test name
Test status
Simulation time 258859427806 ps
CPU time 730.33 seconds
Started Jan 21 09:02:21 PM PST 24
Finished Jan 21 09:14:45 PM PST 24
Peak memory 200596 kb
Host smart-4e8215f2-fffe-4a8f-8f6d-2e2b0048e27f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338590974 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1338590974
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1260302538
Short name T31
Test name
Test status
Simulation time 8095918321 ps
CPU time 7.8 seconds
Started Jan 21 09:01:51 PM PST 24
Finished Jan 21 09:02:14 PM PST 24
Peak memory 215348 kb
Host smart-c502e5c7-6feb-40f1-ad67-d33d48554693
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260302538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1260302538
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2363402577
Short name T106
Test name
Test status
Simulation time 126118409535 ps
CPU time 43.61 seconds
Started Jan 21 09:02:31 PM PST 24
Finished Jan 21 09:03:24 PM PST 24
Peak memory 194204 kb
Host smart-0d78431f-ebbd-455a-b11c-c4a6a6852a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363402577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2363402577
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3654776758
Short name T204
Test name
Test status
Simulation time 9680557734 ps
CPU time 71.91 seconds
Started Jan 21 09:02:30 PM PST 24
Finished Jan 21 09:03:52 PM PST 24
Peak memory 198012 kb
Host smart-8d9708be-e38a-4373-8841-3266642bfc4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654776758 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3654776758
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1001165377
Short name T78
Test name
Test status
Simulation time 9348210486 ps
CPU time 1.79 seconds
Started Jan 21 08:58:50 PM PST 24
Finished Jan 21 08:59:18 PM PST 24
Peak memory 197396 kb
Host smart-81924a8b-25b1-4274-83bd-7585f9c4c84f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001165377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1001165377
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2115136908
Short name T74
Test name
Test status
Simulation time 356054131 ps
CPU time 1.02 seconds
Started Jan 21 08:58:49 PM PST 24
Finished Jan 21 08:59:17 PM PST 24
Peak memory 183512 kb
Host smart-8ebbaffa-b569-4403-8acd-a4e410c08dd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115136908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2115136908
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1886913976
Short name T286
Test name
Test status
Simulation time 427168147970 ps
CPU time 74.8 seconds
Started Jan 21 09:02:27 PM PST 24
Finished Jan 21 09:03:53 PM PST 24
Peak memory 190264 kb
Host smart-4843b0d9-509d-4067-80bb-e2404d7c8370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886913976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1886913976
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1796827419
Short name T12
Test name
Test status
Simulation time 479232671 ps
CPU time 0.85 seconds
Started Jan 21 08:58:52 PM PST 24
Finished Jan 21 08:59:19 PM PST 24
Peak memory 192700 kb
Host smart-d7b96524-1fb1-455f-ab32-2512fd3a4800
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796827419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1796827419
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.212698798
Short name T4
Test name
Test status
Simulation time 10957895266 ps
CPU time 6.13 seconds
Started Jan 21 08:58:54 PM PST 24
Finished Jan 21 08:59:26 PM PST 24
Peak memory 192020 kb
Host smart-00f1d0de-53ba-49a0-ad01-3068c1dc27c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212698798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.212698798
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.768624604
Short name T47
Test name
Test status
Simulation time 755416621 ps
CPU time 0.83 seconds
Started Jan 21 08:58:53 PM PST 24
Finished Jan 21 08:59:20 PM PST 24
Peak memory 183324 kb
Host smart-15b34d7f-9d3d-4ba9-9d35-2d82bf75cff5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768624604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.768624604
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1990593414
Short name T396
Test name
Test status
Simulation time 619813183 ps
CPU time 1.61 seconds
Started Jan 21 08:58:48 PM PST 24
Finished Jan 21 08:59:17 PM PST 24
Peak memory 195204 kb
Host smart-5022e24a-94d7-4f5e-b64f-0e3394e0787a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990593414 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1990593414
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1775449782
Short name T379
Test name
Test status
Simulation time 281803873 ps
CPU time 0.93 seconds
Started Jan 21 08:58:46 PM PST 24
Finished Jan 21 08:59:15 PM PST 24
Peak memory 183184 kb
Host smart-2a355538-f01c-4595-bc9e-79a8a81868ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775449782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1775449782
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.35498783
Short name T318
Test name
Test status
Simulation time 301718308 ps
CPU time 0.62 seconds
Started Jan 21 08:58:50 PM PST 24
Finished Jan 21 08:59:17 PM PST 24
Peak memory 183212 kb
Host smart-8b825fed-7fd6-4929-9818-8fd914424fd4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35498783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim
er_mem_partial_access.35498783
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4241866859
Short name T368
Test name
Test status
Simulation time 309422067 ps
CPU time 0.98 seconds
Started Jan 21 08:58:48 PM PST 24
Finished Jan 21 08:59:16 PM PST 24
Peak memory 183156 kb
Host smart-31df52e2-e0fc-47ae-a992-fb7d42d2b9f4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241866859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.4241866859
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3679676340
Short name T376
Test name
Test status
Simulation time 1142199380 ps
CPU time 2.84 seconds
Started Jan 21 08:58:53 PM PST 24
Finished Jan 21 08:59:21 PM PST 24
Peak memory 193904 kb
Host smart-68803580-e785-4e18-aba3-580b9dda43ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679676340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3679676340
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2008809648
Short name T411
Test name
Test status
Simulation time 543689868 ps
CPU time 2.15 seconds
Started Jan 21 08:58:44 PM PST 24
Finished Jan 21 08:59:15 PM PST 24
Peak memory 198328 kb
Host smart-d3aff507-ff7b-4731-9433-26462304f64b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008809648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2008809648
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2038645190
Short name T391
Test name
Test status
Simulation time 391164587 ps
CPU time 1.06 seconds
Started Jan 21 08:58:57 PM PST 24
Finished Jan 21 08:59:24 PM PST 24
Peak memory 192788 kb
Host smart-766ef535-08e9-4e51-91c0-6a841296efe6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038645190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2038645190
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3215295146
Short name T7
Test name
Test status
Simulation time 6109069687 ps
CPU time 8 seconds
Started Jan 21 08:58:59 PM PST 24
Finished Jan 21 08:59:33 PM PST 24
Peak memory 192020 kb
Host smart-9b87d250-6601-4cf0-9e3c-e838a2d5565f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215295146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3215295146
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2292663639
Short name T66
Test name
Test status
Simulation time 793614010 ps
CPU time 1.17 seconds
Started Jan 21 08:58:56 PM PST 24
Finished Jan 21 08:59:22 PM PST 24
Peak memory 183408 kb
Host smart-fb52c7f4-38c5-4e47-a843-784865bfe8aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292663639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2292663639
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1430785787
Short name T328
Test name
Test status
Simulation time 519702458 ps
CPU time 0.79 seconds
Started Jan 21 08:58:58 PM PST 24
Finished Jan 21 08:59:24 PM PST 24
Peak memory 194492 kb
Host smart-8e8c622e-9f71-471c-99d6-3606d4d05219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430785787 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1430785787
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.283359458
Short name T393
Test name
Test status
Simulation time 519976150 ps
CPU time 0.64 seconds
Started Jan 21 08:58:59 PM PST 24
Finished Jan 21 08:59:25 PM PST 24
Peak memory 183472 kb
Host smart-7d638e1c-4f4a-4a38-b6c8-9fe433a8fe6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283359458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.283359458
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3772901051
Short name T59
Test name
Test status
Simulation time 341010717 ps
CPU time 0.67 seconds
Started Jan 21 08:58:48 PM PST 24
Finished Jan 21 08:59:16 PM PST 24
Peak memory 183180 kb
Host smart-64406410-e04b-44e6-8302-1b2163f70d67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772901051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3772901051
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.138345248
Short name T44
Test name
Test status
Simulation time 485873557 ps
CPU time 1.24 seconds
Started Jan 21 08:58:58 PM PST 24
Finished Jan 21 08:59:25 PM PST 24
Peak memory 183208 kb
Host smart-46c5ddae-108f-428c-9250-887aeaa57c32
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138345248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.138345248
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.150825967
Short name T350
Test name
Test status
Simulation time 305943977 ps
CPU time 0.62 seconds
Started Jan 21 08:58:54 PM PST 24
Finished Jan 21 08:59:20 PM PST 24
Peak memory 183192 kb
Host smart-27f3e0c5-0209-43b7-b218-1d3603afc189
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150825967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.150825967
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3696201973
Short name T335
Test name
Test status
Simulation time 2186446355 ps
CPU time 2.1 seconds
Started Jan 21 10:00:02 PM PST 24
Finished Jan 21 10:00:09 PM PST 24
Peak memory 195044 kb
Host smart-82b17c46-6a31-4c38-a1ad-d40dc53824bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696201973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3696201973
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3508049603
Short name T305
Test name
Test status
Simulation time 484359463 ps
CPU time 1.52 seconds
Started Jan 21 08:58:48 PM PST 24
Finished Jan 21 08:59:16 PM PST 24
Peak memory 198240 kb
Host smart-fd61880d-0e38-4c8a-ac44-680bb5f549aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508049603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3508049603
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3403677719
Short name T319
Test name
Test status
Simulation time 408353726 ps
CPU time 0.78 seconds
Started Jan 21 08:59:35 PM PST 24
Finished Jan 21 08:59:56 PM PST 24
Peak memory 194484 kb
Host smart-7750b124-8160-45bd-993d-d1fc97a97868
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403677719 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3403677719
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3486116871
Short name T358
Test name
Test status
Simulation time 324420949 ps
CPU time 0.85 seconds
Started Jan 21 08:59:35 PM PST 24
Finished Jan 21 08:59:56 PM PST 24
Peak memory 192704 kb
Host smart-99ccfdf5-38b9-4830-8d27-cd5bbf2e3290
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486116871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3486116871
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2716927045
Short name T343
Test name
Test status
Simulation time 462501921 ps
CPU time 0.66 seconds
Started Jan 21 08:59:35 PM PST 24
Finished Jan 21 08:59:55 PM PST 24
Peak memory 183452 kb
Host smart-8d1069ae-fb9d-4aa8-822c-ce78dc5b1e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716927045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2716927045
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.374250612
Short name T75
Test name
Test status
Simulation time 1166810952 ps
CPU time 0.88 seconds
Started Jan 21 08:59:36 PM PST 24
Finished Jan 21 08:59:57 PM PST 24
Peak memory 193284 kb
Host smart-54193486-0c9a-48e8-840c-dd8ea4f67eba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374250612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.374250612
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.535736624
Short name T311
Test name
Test status
Simulation time 395472205 ps
CPU time 1.69 seconds
Started Jan 21 08:59:34 PM PST 24
Finished Jan 21 08:59:56 PM PST 24
Peak memory 198344 kb
Host smart-359fed83-5114-4d08-97fd-be3a3dc0db91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535736624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.535736624
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.599884331
Short name T354
Test name
Test status
Simulation time 4248200358 ps
CPU time 6.98 seconds
Started Jan 21 08:59:36 PM PST 24
Finished Jan 21 09:00:02 PM PST 24
Peak memory 196864 kb
Host smart-a0ab9654-bf1a-43ba-adf7-7e709feed089
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599884331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.599884331
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1375253965
Short name T369
Test name
Test status
Simulation time 572605933 ps
CPU time 1.47 seconds
Started Jan 21 08:59:37 PM PST 24
Finished Jan 21 08:59:59 PM PST 24
Peak memory 195676 kb
Host smart-b79770f7-c993-4769-84ca-169a1bc5e682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375253965 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1375253965
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.778890910
Short name T336
Test name
Test status
Simulation time 363559303 ps
CPU time 0.79 seconds
Started Jan 21 10:47:36 PM PST 24
Finished Jan 21 10:47:39 PM PST 24
Peak memory 183540 kb
Host smart-3b07d13d-078e-499b-884a-92bb8beb72d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778890910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.778890910
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2766047046
Short name T371
Test name
Test status
Simulation time 350262085 ps
CPU time 1 seconds
Started Jan 21 08:59:38 PM PST 24
Finished Jan 21 08:59:59 PM PST 24
Peak memory 183152 kb
Host smart-b2252212-ca6c-4c37-aaae-fedfb4d29025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766047046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2766047046
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4143785463
Short name T1
Test name
Test status
Simulation time 2074838790 ps
CPU time 1.34 seconds
Started Jan 21 08:59:35 PM PST 24
Finished Jan 21 08:59:56 PM PST 24
Peak memory 194440 kb
Host smart-110b7bbc-1ca3-4c3d-9d25-2b03e72cff19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143785463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.4143785463
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.54244699
Short name T365
Test name
Test status
Simulation time 546944341 ps
CPU time 2.78 seconds
Started Jan 21 11:05:56 PM PST 24
Finished Jan 21 11:06:00 PM PST 24
Peak memory 198468 kb
Host smart-7566a39b-b1ca-4e27-809f-98b2ee7fe933
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54244699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.54244699
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1186601030
Short name T352
Test name
Test status
Simulation time 8327965426 ps
CPU time 4.43 seconds
Started Jan 21 08:59:38 PM PST 24
Finished Jan 21 09:00:03 PM PST 24
Peak memory 197432 kb
Host smart-7f717929-acfe-45a0-a9ef-3257dd35ec25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186601030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1186601030
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.563155593
Short name T346
Test name
Test status
Simulation time 331165149 ps
CPU time 1.12 seconds
Started Jan 21 09:32:17 PM PST 24
Finished Jan 21 09:32:37 PM PST 24
Peak memory 194236 kb
Host smart-bf9a0ca2-9703-4bc2-8244-43656efcab05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563155593 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.563155593
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1076941311
Short name T72
Test name
Test status
Simulation time 402609311 ps
CPU time 1.25 seconds
Started Jan 21 08:59:51 PM PST 24
Finished Jan 21 09:00:14 PM PST 24
Peak memory 183276 kb
Host smart-b3385484-ea2b-419e-8778-b4182e014969
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076941311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1076941311
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1498763074
Short name T314
Test name
Test status
Simulation time 280094679 ps
CPU time 0.94 seconds
Started Jan 21 09:20:34 PM PST 24
Finished Jan 21 09:20:36 PM PST 24
Peak memory 183200 kb
Host smart-38b02497-867c-4945-851a-244d3067c09a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498763074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1498763074
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3818727655
Short name T389
Test name
Test status
Simulation time 1208172753 ps
CPU time 0.83 seconds
Started Jan 21 08:59:44 PM PST 24
Finished Jan 21 09:00:04 PM PST 24
Peak memory 193048 kb
Host smart-fa9f4a1c-b399-44a1-b3a2-f521bb16d7f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818727655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3818727655
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.781737890
Short name T402
Test name
Test status
Simulation time 736647843 ps
CPU time 2.02 seconds
Started Jan 21 08:59:35 PM PST 24
Finished Jan 21 08:59:57 PM PST 24
Peak memory 198384 kb
Host smart-c768b8c8-ed89-4d2b-9d34-3072de7a4ce4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781737890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.781737890
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1306867447
Short name T308
Test name
Test status
Simulation time 4945762112 ps
CPU time 2.37 seconds
Started Jan 21 08:59:35 PM PST 24
Finished Jan 21 08:59:57 PM PST 24
Peak memory 195808 kb
Host smart-9f8358e1-5ffe-48cc-a5e0-c76cdcce0741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306867447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1306867447
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2452060077
Short name T364
Test name
Test status
Simulation time 590241847 ps
CPU time 1.55 seconds
Started Jan 21 08:59:49 PM PST 24
Finished Jan 21 09:00:10 PM PST 24
Peak memory 196072 kb
Host smart-7894b148-1873-4623-b980-c632d3e45c4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452060077 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2452060077
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.381407088
Short name T414
Test name
Test status
Simulation time 352664808 ps
CPU time 0.67 seconds
Started Jan 21 08:59:51 PM PST 24
Finished Jan 21 09:00:14 PM PST 24
Peak memory 183300 kb
Host smart-9fc508b5-b716-42f7-ac39-b7df17eb5922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381407088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.381407088
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2556597152
Short name T322
Test name
Test status
Simulation time 346925060 ps
CPU time 1.06 seconds
Started Jan 21 08:59:44 PM PST 24
Finished Jan 21 09:00:03 PM PST 24
Peak memory 183436 kb
Host smart-597fe8c3-e83e-4650-9e91-b6ef1952913d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556597152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2556597152
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2930318009
Short name T320
Test name
Test status
Simulation time 1252992416 ps
CPU time 1.05 seconds
Started Jan 21 08:59:53 PM PST 24
Finished Jan 21 09:00:18 PM PST 24
Peak memory 193820 kb
Host smart-ea90fdb5-a2a7-4ba9-a2cd-092780562e00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930318009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2930318009
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1624724918
Short name T337
Test name
Test status
Simulation time 373959997 ps
CPU time 1.09 seconds
Started Jan 21 08:59:43 PM PST 24
Finished Jan 21 09:00:03 PM PST 24
Peak memory 196384 kb
Host smart-64b6b290-4cc5-4811-b7fb-6f979bddd1e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624724918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1624724918
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3321398388
Short name T412
Test name
Test status
Simulation time 8120661270 ps
CPU time 13.17 seconds
Started Jan 21 08:59:52 PM PST 24
Finished Jan 21 09:00:26 PM PST 24
Peak memory 197196 kb
Host smart-7b7c97c5-00d1-4554-b089-2a0f3cf424cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321398388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3321398388
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.4053464631
Short name T380
Test name
Test status
Simulation time 440345555 ps
CPU time 1.39 seconds
Started Jan 21 08:59:50 PM PST 24
Finished Jan 21 09:00:12 PM PST 24
Peak memory 195536 kb
Host smart-e74e3606-6bf5-4229-99f5-c9bbcd2b2acc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053464631 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.4053464631
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.228054465
Short name T334
Test name
Test status
Simulation time 411388321 ps
CPU time 0.66 seconds
Started Jan 21 08:59:53 PM PST 24
Finished Jan 21 09:00:16 PM PST 24
Peak memory 183408 kb
Host smart-dea4378e-b196-4f60-83d5-500145ba9b70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228054465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.228054465
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1707338055
Short name T15
Test name
Test status
Simulation time 395846255 ps
CPU time 1.11 seconds
Started Jan 21 08:59:49 PM PST 24
Finished Jan 21 09:00:09 PM PST 24
Peak memory 183424 kb
Host smart-93072251-6b4e-469f-a1a2-a2a132f5bb75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707338055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1707338055
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1904730765
Short name T357
Test name
Test status
Simulation time 1689441719 ps
CPU time 3.22 seconds
Started Jan 21 08:59:54 PM PST 24
Finished Jan 21 09:00:22 PM PST 24
Peak memory 193916 kb
Host smart-4f2f1772-a60b-48b0-82ce-0adeed9f2c0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904730765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1904730765
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2944492794
Short name T345
Test name
Test status
Simulation time 522328578 ps
CPU time 1.58 seconds
Started Jan 21 08:59:50 PM PST 24
Finished Jan 21 09:00:12 PM PST 24
Peak memory 198344 kb
Host smart-3bc6779a-63ee-42ab-b844-a442f4ff12aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944492794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2944492794
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2997855777
Short name T395
Test name
Test status
Simulation time 3826340823 ps
CPU time 6.04 seconds
Started Jan 21 08:59:50 PM PST 24
Finished Jan 21 09:00:15 PM PST 24
Peak memory 196808 kb
Host smart-d04de136-7664-4e26-9365-1e51a543fd13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997855777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2997855777
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4123794506
Short name T415
Test name
Test status
Simulation time 585278073 ps
CPU time 0.92 seconds
Started Jan 21 08:59:59 PM PST 24
Finished Jan 21 09:00:26 PM PST 24
Peak memory 195892 kb
Host smart-04b065f4-d3aa-406d-b1fd-5283bfc3ed88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123794506 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.4123794506
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.4182745327
Short name T2
Test name
Test status
Simulation time 485704105 ps
CPU time 0.88 seconds
Started Jan 21 09:00:00 PM PST 24
Finished Jan 21 09:00:27 PM PST 24
Peak memory 183472 kb
Host smart-eb1be98d-7313-45c6-b04a-8fa4bea46ae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182745327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.4182745327
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2792478622
Short name T340
Test name
Test status
Simulation time 385217158 ps
CPU time 0.72 seconds
Started Jan 21 09:00:01 PM PST 24
Finished Jan 21 09:00:28 PM PST 24
Peak memory 183164 kb
Host smart-432c31d6-75dc-4655-8c4a-54d17355a1c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792478622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2792478622
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.428370859
Short name T323
Test name
Test status
Simulation time 1054464297 ps
CPU time 2.71 seconds
Started Jan 21 09:00:01 PM PST 24
Finished Jan 21 09:00:30 PM PST 24
Peak memory 193760 kb
Host smart-9faeb3c0-ccc9-44fe-903f-577fdaded63a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428370859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.428370859
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.165227513
Short name T332
Test name
Test status
Simulation time 541877380 ps
CPU time 2.73 seconds
Started Jan 21 09:00:06 PM PST 24
Finished Jan 21 09:00:36 PM PST 24
Peak memory 198296 kb
Host smart-f0814040-72cc-424a-9903-dfc1e84d28c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165227513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.165227513
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2651885314
Short name T401
Test name
Test status
Simulation time 8403465634 ps
CPU time 3.93 seconds
Started Jan 21 09:00:07 PM PST 24
Finished Jan 21 09:00:39 PM PST 24
Peak memory 197260 kb
Host smart-374da66f-ef26-4cab-b2bd-8b8238780d6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651885314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2651885314
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2992049722
Short name T424
Test name
Test status
Simulation time 562373483 ps
CPU time 0.83 seconds
Started Jan 21 09:00:02 PM PST 24
Finished Jan 21 09:00:29 PM PST 24
Peak memory 194584 kb
Host smart-f859cdfa-fd7b-498d-8b2e-bcaf71a6ce7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992049722 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2992049722
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1093635427
Short name T67
Test name
Test status
Simulation time 490568152 ps
CPU time 0.72 seconds
Started Jan 21 09:00:05 PM PST 24
Finished Jan 21 09:00:33 PM PST 24
Peak memory 183516 kb
Host smart-d513a219-21e3-42cb-a18a-57ec97e99c5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093635427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1093635427
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1198466030
Short name T427
Test name
Test status
Simulation time 509945150 ps
CPU time 1.4 seconds
Started Jan 21 08:59:59 PM PST 24
Finished Jan 21 09:00:27 PM PST 24
Peak memory 183200 kb
Host smart-e2e4582b-aa71-48da-90c1-5730f57f8c75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198466030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1198466030
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2668221160
Short name T374
Test name
Test status
Simulation time 1212619530 ps
CPU time 1.07 seconds
Started Jan 21 09:00:01 PM PST 24
Finished Jan 21 09:00:28 PM PST 24
Peak memory 192912 kb
Host smart-39593f31-7e2b-420f-8f47-5b1c43028336
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668221160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2668221160
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2557020552
Short name T50
Test name
Test status
Simulation time 727094669 ps
CPU time 1.99 seconds
Started Jan 21 09:00:06 PM PST 24
Finished Jan 21 09:00:35 PM PST 24
Peak memory 198292 kb
Host smart-09900705-879f-4509-8666-dc74a06bedd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557020552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2557020552
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.723135598
Short name T80
Test name
Test status
Simulation time 3921688899 ps
CPU time 7.24 seconds
Started Jan 21 09:00:02 PM PST 24
Finished Jan 21 09:00:35 PM PST 24
Peak memory 196856 kb
Host smart-85bb5b76-3db7-4e3a-a89b-85ea9e020dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723135598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.723135598
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1705756816
Short name T17
Test name
Test status
Simulation time 515121925 ps
CPU time 1.45 seconds
Started Jan 21 09:00:07 PM PST 24
Finished Jan 21 09:00:36 PM PST 24
Peak memory 195528 kb
Host smart-e6a0351f-d66d-4cfd-acae-18a4ce5bd40e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705756816 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1705756816
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3743054917
Short name T349
Test name
Test status
Simulation time 403623014 ps
CPU time 0.94 seconds
Started Jan 21 09:00:00 PM PST 24
Finished Jan 21 09:00:27 PM PST 24
Peak memory 183536 kb
Host smart-f661c68f-4179-41a4-8e9d-7cd8d2dc4ee1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743054917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3743054917
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.611966079
Short name T14
Test name
Test status
Simulation time 304819486 ps
CPU time 0.65 seconds
Started Jan 21 09:00:02 PM PST 24
Finished Jan 21 09:00:29 PM PST 24
Peak memory 183440 kb
Host smart-9a7cd294-6304-4bc9-b959-6a257bcb7d30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611966079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.611966079
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3968658080
Short name T76
Test name
Test status
Simulation time 1689734888 ps
CPU time 2.06 seconds
Started Jan 21 09:00:08 PM PST 24
Finished Jan 21 09:00:37 PM PST 24
Peak memory 194952 kb
Host smart-1e09dc64-bd38-41c7-b591-cafdf67a5003
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968658080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3968658080
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.4060456341
Short name T372
Test name
Test status
Simulation time 1297914113 ps
CPU time 2.48 seconds
Started Jan 21 09:00:02 PM PST 24
Finished Jan 21 09:00:31 PM PST 24
Peak memory 198288 kb
Host smart-416ce792-6fb7-4d51-8af0-8dd0941d683a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060456341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.4060456341
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4066395957
Short name T8
Test name
Test status
Simulation time 4900274152 ps
CPU time 2.74 seconds
Started Jan 21 09:00:05 PM PST 24
Finished Jan 21 09:00:34 PM PST 24
Peak memory 196932 kb
Host smart-8f65943f-fc9f-4fe4-b008-12225f10f6fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066395957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.4066395957
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.319941379
Short name T418
Test name
Test status
Simulation time 587335204 ps
CPU time 1.03 seconds
Started Jan 21 09:00:09 PM PST 24
Finished Jan 21 09:00:38 PM PST 24
Peak memory 195136 kb
Host smart-1cc70713-bd5c-41e7-9295-4b0c52017382
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319941379 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.319941379
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.462231973
Short name T425
Test name
Test status
Simulation time 545521296 ps
CPU time 0.77 seconds
Started Jan 21 09:00:09 PM PST 24
Finished Jan 21 09:00:38 PM PST 24
Peak memory 183500 kb
Host smart-5c2b5290-e035-4938-b2ce-cad33ae243d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462231973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.462231973
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.597066636
Short name T18
Test name
Test status
Simulation time 443187266 ps
CPU time 0.7 seconds
Started Jan 21 09:00:07 PM PST 24
Finished Jan 21 09:00:36 PM PST 24
Peak memory 183404 kb
Host smart-6d3f9230-35ee-4f39-bcca-1ba7bc56df56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597066636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.597066636
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2704922828
Short name T351
Test name
Test status
Simulation time 1246203506 ps
CPU time 1 seconds
Started Jan 21 09:45:33 PM PST 24
Finished Jan 21 09:45:36 PM PST 24
Peak memory 194084 kb
Host smart-3f724e3d-5ad0-40f6-90d2-e8d180226e19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704922828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2704922828
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1225737185
Short name T420
Test name
Test status
Simulation time 670274421 ps
CPU time 2.44 seconds
Started Jan 21 09:00:07 PM PST 24
Finished Jan 21 09:00:37 PM PST 24
Peak memory 198360 kb
Host smart-876f4711-91fc-4179-be1a-1a1d69586098
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225737185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1225737185
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1817302382
Short name T405
Test name
Test status
Simulation time 8890910341 ps
CPU time 2.89 seconds
Started Jan 21 09:00:06 PM PST 24
Finished Jan 21 09:00:36 PM PST 24
Peak memory 197132 kb
Host smart-98469dfb-bddb-4d11-84df-78d042239c31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817302382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1817302382
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3677808392
Short name T370
Test name
Test status
Simulation time 566206627 ps
CPU time 1.44 seconds
Started Jan 21 09:00:09 PM PST 24
Finished Jan 21 09:00:39 PM PST 24
Peak memory 195476 kb
Host smart-c761a896-f681-4c98-8bb0-a11df0dd71ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677808392 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3677808392
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.879279487
Short name T73
Test name
Test status
Simulation time 525177195 ps
CPU time 1 seconds
Started Jan 21 09:00:07 PM PST 24
Finished Jan 21 09:00:35 PM PST 24
Peak memory 183476 kb
Host smart-1b66cdf4-1699-429f-a2af-53e77579d7d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879279487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.879279487
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3479849724
Short name T362
Test name
Test status
Simulation time 331175712 ps
CPU time 0.65 seconds
Started Jan 21 09:00:08 PM PST 24
Finished Jan 21 09:00:36 PM PST 24
Peak memory 183396 kb
Host smart-a59e8103-c411-4b71-a5bf-3cd82af8ec7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479849724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3479849724
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2186671568
Short name T344
Test name
Test status
Simulation time 876284062 ps
CPU time 1.71 seconds
Started Jan 21 09:17:38 PM PST 24
Finished Jan 21 09:17:43 PM PST 24
Peak memory 192952 kb
Host smart-2e94496b-bdd5-44a8-83c5-2eaba2c7ec71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186671568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2186671568
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4293540982
Short name T303
Test name
Test status
Simulation time 1229033932 ps
CPU time 2.05 seconds
Started Jan 21 09:00:08 PM PST 24
Finished Jan 21 09:00:37 PM PST 24
Peak memory 198316 kb
Host smart-f397f854-6bbb-43f5-b5b3-d8d9afde9dc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293540982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.4293540982
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3721520886
Short name T79
Test name
Test status
Simulation time 4145856867 ps
CPU time 3.97 seconds
Started Jan 21 09:00:06 PM PST 24
Finished Jan 21 09:00:38 PM PST 24
Peak memory 196980 kb
Host smart-d18bd4c7-7e6d-47b4-b80c-b0dcce46d9b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721520886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3721520886
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1150805627
Short name T348
Test name
Test status
Simulation time 449385468 ps
CPU time 1.27 seconds
Started Jan 21 08:59:05 PM PST 24
Finished Jan 21 08:59:32 PM PST 24
Peak memory 193632 kb
Host smart-01569c74-6391-4531-a9aa-9fbaea24fb07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150805627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1150805627
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1899151103
Short name T65
Test name
Test status
Simulation time 2032841848 ps
CPU time 7.81 seconds
Started Jan 21 08:59:07 PM PST 24
Finished Jan 21 08:59:41 PM PST 24
Peak memory 183700 kb
Host smart-a0d9aa16-f10a-4552-ab1d-35efb610a71a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899151103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1899151103
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3845542417
Short name T43
Test name
Test status
Simulation time 613396128 ps
CPU time 1.03 seconds
Started Jan 21 08:59:01 PM PST 24
Finished Jan 21 08:59:28 PM PST 24
Peak memory 183444 kb
Host smart-4a26cc9e-ac37-41a7-b150-71000223ac70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845542417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3845542417
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.519829677
Short name T5
Test name
Test status
Simulation time 323668227 ps
CPU time 1.1 seconds
Started Jan 21 08:59:06 PM PST 24
Finished Jan 21 08:59:33 PM PST 24
Peak memory 194364 kb
Host smart-9ac405dc-b0da-4f56-9422-18e5972bd016
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519829677 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.519829677
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.476246162
Short name T68
Test name
Test status
Simulation time 449693614 ps
CPU time 1.28 seconds
Started Jan 21 08:59:12 PM PST 24
Finished Jan 21 08:59:38 PM PST 24
Peak memory 183504 kb
Host smart-08b2eb9f-4736-46c9-81a0-ffc5e9b24c44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476246162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.476246162
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1336383921
Short name T58
Test name
Test status
Simulation time 389865077 ps
CPU time 1.05 seconds
Started Jan 21 08:58:57 PM PST 24
Finished Jan 21 08:59:24 PM PST 24
Peak memory 183196 kb
Host smart-3dccf5ee-85ff-4ae4-9543-99c743d0781f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336383921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1336383921
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.882359399
Short name T353
Test name
Test status
Simulation time 452177316 ps
CPU time 1.08 seconds
Started Jan 21 08:59:09 PM PST 24
Finished Jan 21 08:59:36 PM PST 24
Peak memory 183540 kb
Host smart-960e9710-7877-4934-9fea-e88b8257836d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882359399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.882359399
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2581649532
Short name T377
Test name
Test status
Simulation time 535889115 ps
CPU time 0.71 seconds
Started Jan 21 08:59:04 PM PST 24
Finished Jan 21 08:59:30 PM PST 24
Peak memory 183192 kb
Host smart-bc37a05d-bded-4cb0-a6e0-6e0738e3260e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581649532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2581649532
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1441805208
Short name T325
Test name
Test status
Simulation time 1278434779 ps
CPU time 0.85 seconds
Started Jan 21 08:59:09 PM PST 24
Finished Jan 21 08:59:35 PM PST 24
Peak memory 193944 kb
Host smart-a8b5cc0d-85da-44bd-a17e-3faddc5b14b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441805208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1441805208
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1171267893
Short name T421
Test name
Test status
Simulation time 296804975 ps
CPU time 2.33 seconds
Started Jan 21 08:58:58 PM PST 24
Finished Jan 21 08:59:26 PM PST 24
Peak memory 198336 kb
Host smart-f06b6a98-beff-4826-b880-69735a1d8078
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171267893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1171267893
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1715086213
Short name T400
Test name
Test status
Simulation time 7674289106 ps
CPU time 3.75 seconds
Started Jan 21 08:59:01 PM PST 24
Finished Jan 21 08:59:31 PM PST 24
Peak memory 197280 kb
Host smart-e6167116-eea9-447f-acc3-2b250bd4fd6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715086213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1715086213
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2638021555
Short name T410
Test name
Test status
Simulation time 510246620 ps
CPU time 1.12 seconds
Started Jan 21 09:00:09 PM PST 24
Finished Jan 21 09:00:37 PM PST 24
Peak memory 183156 kb
Host smart-2ce75948-e8fe-438f-b125-59ee06d042a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638021555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2638021555
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2766494191
Short name T302
Test name
Test status
Simulation time 481779711 ps
CPU time 1.26 seconds
Started Jan 21 09:00:06 PM PST 24
Finished Jan 21 09:00:34 PM PST 24
Peak memory 183124 kb
Host smart-27b174ab-bded-447a-9ac5-304b75f79635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766494191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2766494191
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.956844160
Short name T329
Test name
Test status
Simulation time 493952992 ps
CPU time 1.31 seconds
Started Jan 21 09:00:08 PM PST 24
Finished Jan 21 09:00:37 PM PST 24
Peak memory 183200 kb
Host smart-8c8c71fb-d1aa-42f4-88f7-817ae4a2ea7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956844160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.956844160
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3593726081
Short name T378
Test name
Test status
Simulation time 401955541 ps
CPU time 0.68 seconds
Started Jan 21 09:00:08 PM PST 24
Finished Jan 21 09:00:37 PM PST 24
Peak memory 183196 kb
Host smart-4ec4912d-804d-467a-a0c2-7440a2eeadce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593726081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3593726081
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3381685574
Short name T339
Test name
Test status
Simulation time 538187351 ps
CPU time 0.65 seconds
Started Jan 21 09:00:08 PM PST 24
Finished Jan 21 09:00:36 PM PST 24
Peak memory 183184 kb
Host smart-b2a491b8-cdfc-42c8-90d3-ea0ac40b4137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381685574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3381685574
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1608458242
Short name T315
Test name
Test status
Simulation time 304505166 ps
CPU time 0.98 seconds
Started Jan 21 09:00:09 PM PST 24
Finished Jan 21 09:00:38 PM PST 24
Peak memory 182984 kb
Host smart-c3d59483-cf9f-489b-9af0-56c5a1c64f5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608458242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1608458242
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2433621297
Short name T404
Test name
Test status
Simulation time 493518572 ps
CPU time 1.34 seconds
Started Jan 21 10:12:18 PM PST 24
Finished Jan 21 10:12:21 PM PST 24
Peak memory 183448 kb
Host smart-4fcd8ffb-d105-422d-8ae7-34bcce402c51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433621297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2433621297
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4044604177
Short name T367
Test name
Test status
Simulation time 507358469 ps
CPU time 1.27 seconds
Started Jan 21 09:00:07 PM PST 24
Finished Jan 21 09:00:36 PM PST 24
Peak memory 183188 kb
Host smart-df64e6d3-f167-49c8-88b0-d3dd0898815d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044604177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.4044604177
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.51641422
Short name T407
Test name
Test status
Simulation time 358544965 ps
CPU time 1.01 seconds
Started Jan 21 09:00:15 PM PST 24
Finished Jan 21 09:00:45 PM PST 24
Peak memory 183112 kb
Host smart-ecb6dc41-0d47-4822-ae49-cc0d6fc34e7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51641422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.51641422
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1864567743
Short name T324
Test name
Test status
Simulation time 408660774 ps
CPU time 0.74 seconds
Started Jan 21 09:00:15 PM PST 24
Finished Jan 21 09:00:44 PM PST 24
Peak memory 183436 kb
Host smart-1bc15084-1097-4484-841f-f214de93d8a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864567743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1864567743
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3894759672
Short name T306
Test name
Test status
Simulation time 504452711 ps
CPU time 1.37 seconds
Started Jan 21 08:59:16 PM PST 24
Finished Jan 21 08:59:41 PM PST 24
Peak memory 192668 kb
Host smart-85c081d8-41d5-4fce-b565-288f9e654273
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894759672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3894759672
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3281354875
Short name T398
Test name
Test status
Simulation time 11387240432 ps
CPU time 10.58 seconds
Started Jan 21 08:59:07 PM PST 24
Finished Jan 21 08:59:43 PM PST 24
Peak memory 195348 kb
Host smart-0d93725e-16fc-49f0-a8b0-0a30fb279c6b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281354875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3281354875
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2894507697
Short name T45
Test name
Test status
Simulation time 694707912 ps
CPU time 1.66 seconds
Started Jan 21 08:59:08 PM PST 24
Finished Jan 21 08:59:35 PM PST 24
Peak memory 183528 kb
Host smart-2124c439-5717-48d4-806e-5692db5e0619
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894507697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2894507697
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1214742727
Short name T387
Test name
Test status
Simulation time 532510522 ps
CPU time 1.05 seconds
Started Jan 21 08:59:16 PM PST 24
Finished Jan 21 08:59:40 PM PST 24
Peak memory 195408 kb
Host smart-ec0c0dd1-1739-49cd-b2f8-105d2ef15d61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214742727 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1214742727
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.889137057
Short name T388
Test name
Test status
Simulation time 540547242 ps
CPU time 0.74 seconds
Started Jan 21 08:59:07 PM PST 24
Finished Jan 21 08:59:34 PM PST 24
Peak memory 183436 kb
Host smart-8751d6f2-a526-459d-8ffd-984594270731
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889137057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.889137057
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4263086254
Short name T422
Test name
Test status
Simulation time 428752341 ps
CPU time 0.91 seconds
Started Jan 21 08:59:08 PM PST 24
Finished Jan 21 08:59:34 PM PST 24
Peak memory 183200 kb
Host smart-da14ac91-1f01-4336-8072-a5cae8814b25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263086254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.4263086254
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2589200203
Short name T347
Test name
Test status
Simulation time 437586857 ps
CPU time 0.86 seconds
Started Jan 21 08:59:10 PM PST 24
Finished Jan 21 08:59:37 PM PST 24
Peak memory 183448 kb
Host smart-bbf6af9e-7ed5-4146-9f94-f195a9ba0def
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589200203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2589200203
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2452723177
Short name T48
Test name
Test status
Simulation time 439403321 ps
CPU time 0.88 seconds
Started Jan 21 08:59:07 PM PST 24
Finished Jan 21 08:59:34 PM PST 24
Peak memory 183468 kb
Host smart-e7a85146-1e93-4d46-aa53-da60ae3fd97a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452723177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2452723177
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2924133369
Short name T11
Test name
Test status
Simulation time 1851716995 ps
CPU time 1.98 seconds
Started Jan 21 08:59:14 PM PST 24
Finished Jan 21 08:59:40 PM PST 24
Peak memory 193720 kb
Host smart-3a64e659-359e-4ba7-b57b-0076864d9650
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924133369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2924133369
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2553281795
Short name T333
Test name
Test status
Simulation time 428046862 ps
CPU time 2.77 seconds
Started Jan 21 08:59:05 PM PST 24
Finished Jan 21 08:59:34 PM PST 24
Peak memory 198216 kb
Host smart-d2020cd7-9649-474f-b157-bb1d39a38a90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553281795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2553281795
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2028389033
Short name T10
Test name
Test status
Simulation time 3867133004 ps
CPU time 1.91 seconds
Started Jan 21 08:59:05 PM PST 24
Finished Jan 21 08:59:33 PM PST 24
Peak memory 195796 kb
Host smart-c8f54ede-d8bb-4948-a807-a073ba115348
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028389033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2028389033
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.499847050
Short name T423
Test name
Test status
Simulation time 296285130 ps
CPU time 0.63 seconds
Started Jan 21 09:00:19 PM PST 24
Finished Jan 21 09:00:48 PM PST 24
Peak memory 183204 kb
Host smart-68c0b955-782f-4b61-969f-93e5642e7c05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499847050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.499847050
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.4212436231
Short name T307
Test name
Test status
Simulation time 352813641 ps
CPU time 1.06 seconds
Started Jan 21 09:41:28 PM PST 24
Finished Jan 21 09:41:30 PM PST 24
Peak memory 183204 kb
Host smart-797579bf-6ec4-484b-a666-2f1e820ddd1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212436231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.4212436231
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3263487402
Short name T331
Test name
Test status
Simulation time 443935761 ps
CPU time 1.06 seconds
Started Jan 21 09:00:22 PM PST 24
Finished Jan 21 09:00:50 PM PST 24
Peak memory 183204 kb
Host smart-435a90e6-5f81-4c88-9845-d69b51c36e1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263487402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3263487402
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3477730829
Short name T356
Test name
Test status
Simulation time 368407101 ps
CPU time 0.68 seconds
Started Jan 21 09:00:22 PM PST 24
Finished Jan 21 09:00:50 PM PST 24
Peak memory 183204 kb
Host smart-5d59e003-5f0f-415b-a679-adf43bb7219f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477730829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3477730829
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1196044979
Short name T390
Test name
Test status
Simulation time 516978867 ps
CPU time 0.99 seconds
Started Jan 21 09:00:17 PM PST 24
Finished Jan 21 09:00:46 PM PST 24
Peak memory 183452 kb
Host smart-d177b9a3-af0f-4b3c-8d70-ff67fa786aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196044979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1196044979
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2093875064
Short name T310
Test name
Test status
Simulation time 311848345 ps
CPU time 0.79 seconds
Started Jan 21 09:00:18 PM PST 24
Finished Jan 21 09:00:46 PM PST 24
Peak memory 183160 kb
Host smart-63fd8066-5a79-44d4-b783-dae7baac3694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093875064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2093875064
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.4127842747
Short name T321
Test name
Test status
Simulation time 305093949 ps
CPU time 0.76 seconds
Started Jan 21 09:00:15 PM PST 24
Finished Jan 21 09:00:44 PM PST 24
Peak memory 183364 kb
Host smart-f552f521-021e-4ac6-bb3a-08b5b5462e56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127842747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.4127842747
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1029012959
Short name T406
Test name
Test status
Simulation time 314091296 ps
CPU time 0.62 seconds
Started Jan 21 09:00:18 PM PST 24
Finished Jan 21 09:00:46 PM PST 24
Peak memory 183140 kb
Host smart-4cf50fce-2503-4d7e-a6b5-4f0e4a17c00c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029012959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1029012959
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.716864352
Short name T316
Test name
Test status
Simulation time 403838484 ps
CPU time 0.7 seconds
Started Jan 21 09:00:18 PM PST 24
Finished Jan 21 09:00:47 PM PST 24
Peak memory 183436 kb
Host smart-b3490630-909d-4338-878c-f59a60bfb17f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716864352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.716864352
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3533391335
Short name T416
Test name
Test status
Simulation time 324176344 ps
CPU time 0.79 seconds
Started Jan 21 09:07:12 PM PST 24
Finished Jan 21 09:07:27 PM PST 24
Peak memory 183452 kb
Host smart-189ca1d0-b1ab-4fe9-afe3-c981edf4146a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533391335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3533391335
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.333065954
Short name T71
Test name
Test status
Simulation time 520223481 ps
CPU time 1.22 seconds
Started Jan 21 08:59:18 PM PST 24
Finished Jan 21 08:59:42 PM PST 24
Peak memory 192928 kb
Host smart-098b37d8-e750-4a46-ba37-0b47360fa509
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333065954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.333065954
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.363177574
Short name T46
Test name
Test status
Simulation time 659273428 ps
CPU time 1.49 seconds
Started Jan 21 08:59:19 PM PST 24
Finished Jan 21 08:59:44 PM PST 24
Peak memory 183492 kb
Host smart-59892f41-8f45-4d8e-b20d-c7cb6977d6e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363177574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.363177574
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.536878226
Short name T382
Test name
Test status
Simulation time 400996445 ps
CPU time 0.81 seconds
Started Jan 21 08:59:15 PM PST 24
Finished Jan 21 08:59:40 PM PST 24
Peak memory 194748 kb
Host smart-e5ba7659-348d-4f10-ba26-10163e65b0b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536878226 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.536878226
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.147712213
Short name T64
Test name
Test status
Simulation time 476708811 ps
CPU time 0.73 seconds
Started Jan 21 08:59:19 PM PST 24
Finished Jan 21 08:59:43 PM PST 24
Peak memory 183476 kb
Host smart-84e1e5d8-1d77-424b-bfac-d58ac5ec8992
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147712213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.147712213
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.825825942
Short name T309
Test name
Test status
Simulation time 310907209 ps
CPU time 1.03 seconds
Started Jan 21 08:59:19 PM PST 24
Finished Jan 21 08:59:43 PM PST 24
Peak memory 183384 kb
Host smart-88cd9f13-5385-459b-bf9c-1a2727ef7a6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825825942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.825825942
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.70630945
Short name T385
Test name
Test status
Simulation time 442912296 ps
CPU time 1.2 seconds
Started Jan 21 08:59:18 PM PST 24
Finished Jan 21 08:59:43 PM PST 24
Peak memory 183472 kb
Host smart-d1a237b9-522d-4db3-8538-bd4e604eb41b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70630945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_tim
er_mem_partial_access.70630945
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3291013005
Short name T49
Test name
Test status
Simulation time 487926033 ps
CPU time 0.66 seconds
Started Jan 21 08:59:15 PM PST 24
Finished Jan 21 08:59:40 PM PST 24
Peak memory 183172 kb
Host smart-1bcb6e99-caf6-4110-b6be-a5abd74764a9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291013005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3291013005
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.514071192
Short name T403
Test name
Test status
Simulation time 2545641461 ps
CPU time 5.85 seconds
Started Jan 21 08:59:15 PM PST 24
Finished Jan 21 08:59:44 PM PST 24
Peak memory 195072 kb
Host smart-ef08a941-8c6e-4c57-bf6c-e09f8f228616
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514071192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.514071192
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2432264028
Short name T304
Test name
Test status
Simulation time 597389860 ps
CPU time 2.65 seconds
Started Jan 21 08:59:19 PM PST 24
Finished Jan 21 08:59:45 PM PST 24
Peak memory 198336 kb
Host smart-26732c27-2124-4474-8181-9d72d4defe0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432264028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2432264028
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3928248301
Short name T373
Test name
Test status
Simulation time 4600285316 ps
CPU time 6.85 seconds
Started Jan 21 08:59:19 PM PST 24
Finished Jan 21 08:59:49 PM PST 24
Peak memory 196680 kb
Host smart-3f30e87e-625b-49cf-b6ea-a22a747c132b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928248301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3928248301
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4000806080
Short name T16
Test name
Test status
Simulation time 333654511 ps
CPU time 0.61 seconds
Started Jan 21 09:00:23 PM PST 24
Finished Jan 21 09:00:51 PM PST 24
Peak memory 183112 kb
Host smart-e3651ea3-078f-4aef-9f1a-54d7c0880c59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000806080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.4000806080
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1068772687
Short name T392
Test name
Test status
Simulation time 412022496 ps
CPU time 0.66 seconds
Started Jan 21 09:00:25 PM PST 24
Finished Jan 21 09:00:53 PM PST 24
Peak memory 183400 kb
Host smart-79764682-6a9c-474f-a159-711599075fa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068772687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1068772687
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2658303041
Short name T428
Test name
Test status
Simulation time 427092971 ps
CPU time 0.72 seconds
Started Jan 21 09:00:28 PM PST 24
Finished Jan 21 09:00:55 PM PST 24
Peak memory 183180 kb
Host smart-016c3605-0f6f-4ae6-b842-02fca5ee831c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658303041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2658303041
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3412954709
Short name T409
Test name
Test status
Simulation time 282397006 ps
CPU time 1 seconds
Started Jan 21 09:00:26 PM PST 24
Finished Jan 21 09:00:55 PM PST 24
Peak memory 183144 kb
Host smart-6ab56497-2b7c-4ee9-a0ec-75499c7f87dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412954709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3412954709
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3560617798
Short name T341
Test name
Test status
Simulation time 297852344 ps
CPU time 0.64 seconds
Started Jan 21 09:00:29 PM PST 24
Finished Jan 21 09:00:58 PM PST 24
Peak memory 183184 kb
Host smart-f152f189-192b-4283-a418-51461bbf0a4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560617798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3560617798
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3876704856
Short name T366
Test name
Test status
Simulation time 310161113 ps
CPU time 1 seconds
Started Jan 21 09:00:25 PM PST 24
Finished Jan 21 09:00:53 PM PST 24
Peak memory 183196 kb
Host smart-5bbb2fdb-3072-4b10-b636-bdc84d64e9dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876704856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3876704856
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3448240969
Short name T327
Test name
Test status
Simulation time 338865606 ps
CPU time 0.67 seconds
Started Jan 21 09:00:24 PM PST 24
Finished Jan 21 09:00:52 PM PST 24
Peak memory 183632 kb
Host smart-2111acb4-a488-4c0e-a943-25f7fae2dfd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448240969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3448240969
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.945174496
Short name T383
Test name
Test status
Simulation time 363115214 ps
CPU time 1.09 seconds
Started Jan 21 09:00:26 PM PST 24
Finished Jan 21 09:00:54 PM PST 24
Peak memory 183212 kb
Host smart-8bcd81bf-ad6d-4815-9504-f45d7467afc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945174496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.945174496
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.893156802
Short name T312
Test name
Test status
Simulation time 350760215 ps
CPU time 0.68 seconds
Started Jan 21 09:00:23 PM PST 24
Finished Jan 21 09:00:51 PM PST 24
Peak memory 183204 kb
Host smart-ef05b18b-4b32-408f-a8e5-f922c78bb1bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893156802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.893156802
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3805820288
Short name T313
Test name
Test status
Simulation time 417041742 ps
CPU time 1.1 seconds
Started Jan 21 09:00:24 PM PST 24
Finished Jan 21 09:00:52 PM PST 24
Peak memory 183140 kb
Host smart-3e27b82d-fc03-4123-859e-246d82d14aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805820288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3805820288
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1544039640
Short name T426
Test name
Test status
Simulation time 511728869 ps
CPU time 1.35 seconds
Started Jan 21 08:59:26 PM PST 24
Finished Jan 21 08:59:49 PM PST 24
Peak memory 195140 kb
Host smart-f9e39819-d3a3-40a9-8d4d-5981c31fc79f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544039640 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1544039640
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3170443390
Short name T338
Test name
Test status
Simulation time 503950358 ps
CPU time 1.4 seconds
Started Jan 21 08:59:19 PM PST 24
Finished Jan 21 08:59:44 PM PST 24
Peak memory 183452 kb
Host smart-e6eb7464-852d-4b3b-b5b3-5234ee536bd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170443390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3170443390
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1623927068
Short name T384
Test name
Test status
Simulation time 428163948 ps
CPU time 1.01 seconds
Started Jan 21 08:59:13 PM PST 24
Finished Jan 21 08:59:38 PM PST 24
Peak memory 183152 kb
Host smart-18d4a52f-b764-47f9-b13d-8570c7007941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623927068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1623927068
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1915938765
Short name T417
Test name
Test status
Simulation time 1940741944 ps
CPU time 1.61 seconds
Started Jan 21 08:59:19 PM PST 24
Finished Jan 21 08:59:44 PM PST 24
Peak memory 194184 kb
Host smart-985cc339-849f-4e38-a556-92b5b386397f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915938765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1915938765
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.82430523
Short name T419
Test name
Test status
Simulation time 446681604 ps
CPU time 2.15 seconds
Started Jan 21 08:59:18 PM PST 24
Finished Jan 21 08:59:44 PM PST 24
Peak memory 198336 kb
Host smart-733503ba-e040-4b51-bc35-002ae2449f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82430523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.82430523
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1182360448
Short name T330
Test name
Test status
Simulation time 4402031140 ps
CPU time 1.59 seconds
Started Jan 21 08:59:24 PM PST 24
Finished Jan 21 08:59:48 PM PST 24
Peak memory 195792 kb
Host smart-ddd597f7-bff7-4548-a070-051e07f1fff5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182360448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1182360448
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.438658660
Short name T394
Test name
Test status
Simulation time 432969846 ps
CPU time 0.83 seconds
Started Jan 21 08:59:21 PM PST 24
Finished Jan 21 08:59:45 PM PST 24
Peak memory 196472 kb
Host smart-386067b6-0109-4aba-920b-bdd558801fd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438658660 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.438658660
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3666504815
Short name T359
Test name
Test status
Simulation time 358150445 ps
CPU time 0.68 seconds
Started Jan 21 08:59:23 PM PST 24
Finished Jan 21 08:59:46 PM PST 24
Peak memory 183520 kb
Host smart-1b62536e-676a-4ebd-90c9-28eace337eef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666504815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3666504815
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.51862951
Short name T360
Test name
Test status
Simulation time 401976316 ps
CPU time 0.66 seconds
Started Jan 21 08:59:19 PM PST 24
Finished Jan 21 08:59:43 PM PST 24
Peak memory 183112 kb
Host smart-2993b7c5-0f5c-48e5-a8a4-da0ae7632791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51862951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.51862951
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1161994677
Short name T361
Test name
Test status
Simulation time 1052094759 ps
CPU time 2.37 seconds
Started Jan 21 08:59:18 PM PST 24
Finished Jan 21 08:59:44 PM PST 24
Peak memory 193888 kb
Host smart-5654230b-0bec-47ce-81af-36eae5717d10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161994677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1161994677
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.853497719
Short name T317
Test name
Test status
Simulation time 310302937 ps
CPU time 1.44 seconds
Started Jan 21 08:59:21 PM PST 24
Finished Jan 21 08:59:46 PM PST 24
Peak memory 198084 kb
Host smart-d629e7ef-7903-442b-95a3-50f8c5731ef2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853497719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.853497719
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1668377535
Short name T413
Test name
Test status
Simulation time 8240973690 ps
CPU time 4.1 seconds
Started Jan 21 08:59:24 PM PST 24
Finished Jan 21 08:59:50 PM PST 24
Peak memory 197156 kb
Host smart-412bf0aa-74ac-4abb-809a-d07ea2060176
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668377535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1668377535
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2622679103
Short name T355
Test name
Test status
Simulation time 387925784 ps
CPU time 0.76 seconds
Started Jan 21 08:59:24 PM PST 24
Finished Jan 21 08:59:48 PM PST 24
Peak memory 194400 kb
Host smart-d5450512-0440-4ffb-be65-16a16bf7c786
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622679103 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2622679103
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.135740278
Short name T69
Test name
Test status
Simulation time 533905944 ps
CPU time 1.34 seconds
Started Jan 21 08:59:29 PM PST 24
Finished Jan 21 08:59:52 PM PST 24
Peak memory 183664 kb
Host smart-ff9b398e-28c7-4a07-a5e5-06eea027f1b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135740278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.135740278
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3102279421
Short name T429
Test name
Test status
Simulation time 440395945 ps
CPU time 0.7 seconds
Started Jan 21 08:59:24 PM PST 24
Finished Jan 21 08:59:48 PM PST 24
Peak memory 183212 kb
Host smart-0c2e6c16-6fbf-47fb-a837-6c9ae4aa8913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102279421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3102279421
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3992797442
Short name T77
Test name
Test status
Simulation time 917586274 ps
CPU time 1.18 seconds
Started Jan 21 08:59:22 PM PST 24
Finished Jan 21 08:59:46 PM PST 24
Peak memory 193960 kb
Host smart-cd53dcce-652c-478c-8195-37037920b435
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992797442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3992797442
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.109487675
Short name T408
Test name
Test status
Simulation time 996727439 ps
CPU time 2.23 seconds
Started Jan 21 08:59:19 PM PST 24
Finished Jan 21 08:59:45 PM PST 24
Peak memory 198244 kb
Host smart-9da08feb-cebe-428a-8c47-2490416d4087
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109487675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.109487675
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1965481812
Short name T375
Test name
Test status
Simulation time 4341769135 ps
CPU time 1.67 seconds
Started Jan 21 08:59:19 PM PST 24
Finished Jan 21 08:59:44 PM PST 24
Peak memory 195536 kb
Host smart-e2ad127b-5368-4e78-9247-ed82af6ff6ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965481812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1965481812
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1485693276
Short name T363
Test name
Test status
Simulation time 523158512 ps
CPU time 0.95 seconds
Started Jan 21 08:59:28 PM PST 24
Finished Jan 21 08:59:50 PM PST 24
Peak memory 197148 kb
Host smart-e1141223-f0ce-4cbb-aa29-18fcb9d57b5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485693276 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1485693276
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1713221744
Short name T70
Test name
Test status
Simulation time 520803502 ps
CPU time 0.93 seconds
Started Jan 21 08:59:21 PM PST 24
Finished Jan 21 08:59:45 PM PST 24
Peak memory 183524 kb
Host smart-2441baf8-7fdf-427d-8724-425467c8f938
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713221744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1713221744
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.384131783
Short name T326
Test name
Test status
Simulation time 400249167 ps
CPU time 0.86 seconds
Started Jan 21 08:59:24 PM PST 24
Finished Jan 21 08:59:48 PM PST 24
Peak memory 183180 kb
Host smart-5c27f51f-1416-4f65-951b-cc57cfa6ae60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384131783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.384131783
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2405755677
Short name T9
Test name
Test status
Simulation time 1312379095 ps
CPU time 0.9 seconds
Started Jan 21 08:59:25 PM PST 24
Finished Jan 21 08:59:48 PM PST 24
Peak memory 193988 kb
Host smart-577cdbe9-9caf-4201-811b-0a1d57156128
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405755677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2405755677
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4002219165
Short name T52
Test name
Test status
Simulation time 752749555 ps
CPU time 1.68 seconds
Started Jan 21 08:59:21 PM PST 24
Finished Jan 21 08:59:46 PM PST 24
Peak memory 198332 kb
Host smart-e9d3b171-dc8d-4261-a80f-237c8a44ed5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002219165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.4002219165
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.674336363
Short name T386
Test name
Test status
Simulation time 4564231933 ps
CPU time 4.51 seconds
Started Jan 21 08:59:20 PM PST 24
Finished Jan 21 08:59:48 PM PST 24
Peak memory 197060 kb
Host smart-060804ce-84c1-49c8-a47a-a859ca9639be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674336363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.674336363
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.737270754
Short name T381
Test name
Test status
Simulation time 415499170 ps
CPU time 0.9 seconds
Started Jan 21 08:59:39 PM PST 24
Finished Jan 21 09:00:00 PM PST 24
Peak memory 196916 kb
Host smart-196887df-1cdd-407f-bb08-7ee50200f24c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737270754 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.737270754
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2499468922
Short name T397
Test name
Test status
Simulation time 416861136 ps
CPU time 0.73 seconds
Started Jan 21 09:13:29 PM PST 24
Finished Jan 21 09:13:32 PM PST 24
Peak memory 183536 kb
Host smart-7539f20b-87e0-4c9d-b6b2-a96a6eec83b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499468922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2499468922
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.990587424
Short name T115
Test name
Test status
Simulation time 382523213 ps
CPU time 0.81 seconds
Started Jan 21 08:59:27 PM PST 24
Finished Jan 21 08:59:50 PM PST 24
Peak memory 183140 kb
Host smart-d8e5affb-3dce-450d-9a86-e038994a9782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990587424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.990587424
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3683070488
Short name T342
Test name
Test status
Simulation time 2442857681 ps
CPU time 3.54 seconds
Started Jan 21 08:59:39 PM PST 24
Finished Jan 21 09:00:02 PM PST 24
Peak memory 195168 kb
Host smart-bd0e7bec-e97c-4bb9-8416-52a2f4eeb80b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683070488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3683070488
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1040774
Short name T399
Test name
Test status
Simulation time 321893058 ps
CPU time 1.7 seconds
Started Jan 21 08:59:22 PM PST 24
Finished Jan 21 08:59:47 PM PST 24
Peak memory 198288 kb
Host smart-d3fd5334-811f-4fac-b945-87c1849cd964
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1040774
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.278670082
Short name T81
Test name
Test status
Simulation time 4367084750 ps
CPU time 2.5 seconds
Started Jan 21 08:59:29 PM PST 24
Finished Jan 21 08:59:53 PM PST 24
Peak memory 196840 kb
Host smart-a8a4ada8-02e2-478a-b42f-9a2b47c0bd60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278670082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.278670082
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2748357529
Short name T280
Test name
Test status
Simulation time 387273696 ps
CPU time 0.68 seconds
Started Jan 21 09:01:50 PM PST 24
Finished Jan 21 09:02:07 PM PST 24
Peak memory 183040 kb
Host smart-4290587f-bf1b-4a0e-93a7-709252dabdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748357529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2748357529
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3164214825
Short name T170
Test name
Test status
Simulation time 28741610283 ps
CPU time 41.27 seconds
Started Jan 21 09:01:57 PM PST 24
Finished Jan 21 09:02:55 PM PST 24
Peak memory 183092 kb
Host smart-5c1428fd-fc7e-4001-bbbd-28757e485d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164214825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3164214825
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3698525311
Short name T128
Test name
Test status
Simulation time 536096818 ps
CPU time 1.26 seconds
Started Jan 21 09:01:51 PM PST 24
Finished Jan 21 09:02:08 PM PST 24
Peak memory 182904 kb
Host smart-84d70a53-898c-4dba-b6c2-5a97421f935f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698525311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3698525311
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2144685445
Short name T38
Test name
Test status
Simulation time 190740825018 ps
CPU time 143.38 seconds
Started Jan 21 09:01:55 PM PST 24
Finished Jan 21 09:04:35 PM PST 24
Peak memory 183128 kb
Host smart-17b30b05-6aab-4191-b8d7-e5f5f97a3790
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144685445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2144685445
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.516432000
Short name T278
Test name
Test status
Simulation time 166712124808 ps
CPU time 513.96 seconds
Started Jan 21 09:01:55 PM PST 24
Finished Jan 21 09:10:46 PM PST 24
Peak memory 197988 kb
Host smart-e5274c80-b437-4662-bb71-6ac30d89daed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516432000 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.516432000
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3521133218
Short name T107
Test name
Test status
Simulation time 395465957 ps
CPU time 1.15 seconds
Started Jan 21 09:01:51 PM PST 24
Finished Jan 21 09:02:08 PM PST 24
Peak memory 183072 kb
Host smart-0bc4493b-dd2b-44b8-9ad1-b21a9fbb3542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521133218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3521133218
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2895922108
Short name T172
Test name
Test status
Simulation time 20455838949 ps
CPU time 15.91 seconds
Started Jan 21 09:01:55 PM PST 24
Finished Jan 21 09:02:28 PM PST 24
Peak memory 183080 kb
Host smart-2d750602-a7cd-4c88-9af1-ba92760fa652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895922108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2895922108
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2792114227
Short name T32
Test name
Test status
Simulation time 4586781011 ps
CPU time 1.55 seconds
Started Jan 21 09:02:03 PM PST 24
Finished Jan 21 09:02:20 PM PST 24
Peak memory 215236 kb
Host smart-50dd3745-7b14-4608-9822-a1a052eb746d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792114227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2792114227
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.397782929
Short name T26
Test name
Test status
Simulation time 484201209 ps
CPU time 1.36 seconds
Started Jan 21 09:01:50 PM PST 24
Finished Jan 21 09:02:08 PM PST 24
Peak memory 182916 kb
Host smart-0c14dbf1-00b6-476a-a538-11297e6f7764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397782929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.397782929
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1129446580
Short name T199
Test name
Test status
Simulation time 168087183981 ps
CPU time 219.4 seconds
Started Jan 21 09:01:59 PM PST 24
Finished Jan 21 09:05:55 PM PST 24
Peak memory 193344 kb
Host smart-fc7de912-94c3-49dd-bae4-144d5716f27e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129446580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1129446580
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2021094629
Short name T190
Test name
Test status
Simulation time 430589242246 ps
CPU time 1077.09 seconds
Started Jan 21 09:02:04 PM PST 24
Finished Jan 21 09:20:16 PM PST 24
Peak memory 205416 kb
Host smart-18a03066-59c9-4ad0-a33d-9b8636211354
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021094629 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2021094629
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.907476531
Short name T262
Test name
Test status
Simulation time 429806827 ps
CPU time 1.17 seconds
Started Jan 21 09:02:17 PM PST 24
Finished Jan 21 09:02:32 PM PST 24
Peak memory 183012 kb
Host smart-59fb2a28-3fb0-4366-b642-d5c87d6c678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907476531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.907476531
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.171812134
Short name T224
Test name
Test status
Simulation time 32249224844 ps
CPU time 12.01 seconds
Started Jan 21 09:02:21 PM PST 24
Finished Jan 21 09:02:46 PM PST 24
Peak memory 183136 kb
Host smart-7ba897b8-b919-4452-86af-c838f68899fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171812134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.171812134
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2032442817
Short name T245
Test name
Test status
Simulation time 522254730 ps
CPU time 1.19 seconds
Started Jan 21 09:02:16 PM PST 24
Finished Jan 21 09:02:32 PM PST 24
Peak memory 182836 kb
Host smart-a04e907f-6f73-4e97-be66-94c1e16014bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032442817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2032442817
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_jump.352833919
Short name T94
Test name
Test status
Simulation time 584480847 ps
CPU time 1.49 seconds
Started Jan 21 09:02:27 PM PST 24
Finished Jan 21 09:02:39 PM PST 24
Peak memory 182208 kb
Host smart-2991c516-7029-4633-a3b0-277f0831da11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352833919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.352833919
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2298246799
Short name T152
Test name
Test status
Simulation time 9164932906 ps
CPU time 4.66 seconds
Started Jan 21 09:02:17 PM PST 24
Finished Jan 21 09:02:36 PM PST 24
Peak memory 183056 kb
Host smart-f016cba7-aba5-4caa-b227-06ae63c4a4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298246799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2298246799
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3899938275
Short name T126
Test name
Test status
Simulation time 534581370 ps
CPU time 0.94 seconds
Started Jan 21 09:02:18 PM PST 24
Finished Jan 21 09:02:33 PM PST 24
Peak memory 182980 kb
Host smart-8eb97f43-009d-4283-98ac-c3f99e116b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899938275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3899938275
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3450133543
Short name T86
Test name
Test status
Simulation time 339338516455 ps
CPU time 268.35 seconds
Started Jan 21 09:02:21 PM PST 24
Finished Jan 21 09:07:03 PM PST 24
Peak memory 194584 kb
Host smart-77d02762-c44a-40ca-8e9e-764bf56e9b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450133543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3450133543
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3244256341
Short name T91
Test name
Test status
Simulation time 152457519697 ps
CPU time 249.66 seconds
Started Jan 21 09:02:17 PM PST 24
Finished Jan 21 09:06:41 PM PST 24
Peak memory 197984 kb
Host smart-1eb299a4-5659-4a07-aef9-35c936a5d9c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244256341 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3244256341
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1521313246
Short name T171
Test name
Test status
Simulation time 622880625 ps
CPU time 1.57 seconds
Started Jan 21 09:02:21 PM PST 24
Finished Jan 21 09:02:36 PM PST 24
Peak memory 183040 kb
Host smart-60ee75cd-b22c-4536-a255-641807c4ad6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521313246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1521313246
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3403697008
Short name T20
Test name
Test status
Simulation time 53522248426 ps
CPU time 18.19 seconds
Started Jan 21 09:02:18 PM PST 24
Finished Jan 21 09:02:50 PM PST 24
Peak memory 183060 kb
Host smart-e315d5a9-488e-486c-a91c-f5769764404c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403697008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3403697008
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1595413079
Short name T118
Test name
Test status
Simulation time 346494953 ps
CPU time 0.79 seconds
Started Jan 21 09:02:21 PM PST 24
Finished Jan 21 09:02:35 PM PST 24
Peak memory 182944 kb
Host smart-6cd2ccb5-195e-4606-95fc-93fecff00018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595413079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1595413079
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3543447301
Short name T269
Test name
Test status
Simulation time 40131866035 ps
CPU time 20.78 seconds
Started Jan 21 09:02:27 PM PST 24
Finished Jan 21 09:02:59 PM PST 24
Peak memory 193196 kb
Host smart-d6c64866-efaa-4ac2-856d-fd14a96dadcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543447301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3543447301
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3910505329
Short name T296
Test name
Test status
Simulation time 344623048 ps
CPU time 1.08 seconds
Started Jan 21 09:02:26 PM PST 24
Finished Jan 21 09:02:38 PM PST 24
Peak memory 183060 kb
Host smart-2d30a9f4-4664-4993-bfe3-0312fc5bf201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910505329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3910505329
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.949991108
Short name T168
Test name
Test status
Simulation time 12230685721 ps
CPU time 19.97 seconds
Started Jan 21 09:02:30 PM PST 24
Finished Jan 21 09:03:00 PM PST 24
Peak memory 183144 kb
Host smart-46039795-56c8-405e-ac04-c5790c915731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949991108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.949991108
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.387140199
Short name T256
Test name
Test status
Simulation time 340139501 ps
CPU time 1.04 seconds
Started Jan 21 09:02:24 PM PST 24
Finished Jan 21 09:02:37 PM PST 24
Peak memory 182852 kb
Host smart-c2180d63-5880-4a27-9e7e-999f31069f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387140199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.387140199
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3902817550
Short name T255
Test name
Test status
Simulation time 239176045570 ps
CPU time 320.77 seconds
Started Jan 21 09:02:28 PM PST 24
Finished Jan 21 09:07:59 PM PST 24
Peak memory 183188 kb
Host smart-67de6267-fcca-48e7-9610-9f300c8dd2c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902817550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3902817550
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3864188159
Short name T97
Test name
Test status
Simulation time 22354598685 ps
CPU time 254.06 seconds
Started Jan 21 09:02:29 PM PST 24
Finished Jan 21 09:06:53 PM PST 24
Peak memory 198004 kb
Host smart-df1daa5b-b42c-43ad-833b-7c21d4a28113
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864188159 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3864188159
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3549886431
Short name T250
Test name
Test status
Simulation time 534543210 ps
CPU time 1.05 seconds
Started Jan 21 09:02:30 PM PST 24
Finished Jan 21 09:02:41 PM PST 24
Peak memory 183060 kb
Host smart-df7b5ddf-1baa-46da-b1a5-13a82d5f760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549886431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3549886431
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.863862417
Short name T184
Test name
Test status
Simulation time 19491560360 ps
CPU time 33.73 seconds
Started Jan 21 09:02:29 PM PST 24
Finished Jan 21 09:03:13 PM PST 24
Peak memory 183196 kb
Host smart-04108e7e-1f29-49f4-b999-8846f38528d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863862417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.863862417
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3397302301
Short name T202
Test name
Test status
Simulation time 478338949 ps
CPU time 0.7 seconds
Started Jan 21 09:02:30 PM PST 24
Finished Jan 21 09:02:41 PM PST 24
Peak memory 182872 kb
Host smart-1c408ade-9928-441f-8de9-d858cc6f4020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397302301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3397302301
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.809753400
Short name T281
Test name
Test status
Simulation time 355395613788 ps
CPU time 92 seconds
Started Jan 21 09:02:27 PM PST 24
Finished Jan 21 09:04:10 PM PST 24
Peak memory 183136 kb
Host smart-635c70f0-c35f-46de-8ef4-29ae5341cae6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809753400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.809753400
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2132763680
Short name T220
Test name
Test status
Simulation time 485819960 ps
CPU time 0.63 seconds
Started Jan 21 09:02:34 PM PST 24
Finished Jan 21 09:02:44 PM PST 24
Peak memory 183064 kb
Host smart-2544edf0-2b98-4d3b-8edd-5b1f49cf33b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132763680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2132763680
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2657973936
Short name T299
Test name
Test status
Simulation time 51265197253 ps
CPU time 76 seconds
Started Jan 21 09:02:35 PM PST 24
Finished Jan 21 09:03:59 PM PST 24
Peak memory 183136 kb
Host smart-2de02e2f-e4a9-43e6-b818-22dc6e6c8780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657973936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2657973936
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2308936096
Short name T275
Test name
Test status
Simulation time 409341296 ps
CPU time 1.17 seconds
Started Jan 21 09:02:37 PM PST 24
Finished Jan 21 09:02:46 PM PST 24
Peak memory 182920 kb
Host smart-2177a08a-0efd-42ae-9bea-858e24fad39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308936096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2308936096
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3568013704
Short name T35
Test name
Test status
Simulation time 585679377579 ps
CPU time 413.83 seconds
Started Jan 21 09:02:32 PM PST 24
Finished Jan 21 09:09:35 PM PST 24
Peak memory 183284 kb
Host smart-5bcee600-e2c9-4d12-b548-fdb4491ec3e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568013704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3568013704
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1430133313
Short name T27
Test name
Test status
Simulation time 259597691502 ps
CPU time 722.07 seconds
Started Jan 21 09:02:32 PM PST 24
Finished Jan 21 09:14:43 PM PST 24
Peak memory 200824 kb
Host smart-ade780fa-493f-4929-877e-63a010d116ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430133313 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1430133313
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3947543148
Short name T100
Test name
Test status
Simulation time 528292754 ps
CPU time 1.31 seconds
Started Jan 21 09:02:31 PM PST 24
Finished Jan 21 09:02:42 PM PST 24
Peak memory 183056 kb
Host smart-d1c83f2d-e79e-47f3-a5e3-4e00bab71670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947543148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3947543148
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.23987243
Short name T222
Test name
Test status
Simulation time 29761617630 ps
CPU time 43.39 seconds
Started Jan 21 09:02:36 PM PST 24
Finished Jan 21 09:03:28 PM PST 24
Peak memory 183180 kb
Host smart-4f424d5b-d319-4be6-93ef-7f42e0a8c7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23987243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.23987243
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.868023310
Short name T258
Test name
Test status
Simulation time 597241268 ps
CPU time 0.75 seconds
Started Jan 21 09:02:39 PM PST 24
Finished Jan 21 09:02:47 PM PST 24
Peak memory 182936 kb
Host smart-6b1700d0-959f-4527-a34f-9f35916a8fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868023310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.868023310
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3587647793
Short name T55
Test name
Test status
Simulation time 442433985730 ps
CPU time 272.95 seconds
Started Jan 21 09:02:32 PM PST 24
Finished Jan 21 09:07:14 PM PST 24
Peak memory 198004 kb
Host smart-32761440-a913-4873-b388-5bb7c6c46490
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587647793 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3587647793
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2897942405
Short name T263
Test name
Test status
Simulation time 464969014 ps
CPU time 0.83 seconds
Started Jan 21 09:02:30 PM PST 24
Finished Jan 21 09:02:41 PM PST 24
Peak memory 183032 kb
Host smart-4d64173f-0f32-422e-a48f-59ad2a6bf869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897942405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2897942405
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.422350146
Short name T131
Test name
Test status
Simulation time 8258305989 ps
CPU time 3.6 seconds
Started Jan 21 09:02:32 PM PST 24
Finished Jan 21 09:02:45 PM PST 24
Peak memory 183144 kb
Host smart-a2fde688-1d56-43b6-a2d0-9af7a6532cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422350146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.422350146
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.4010825481
Short name T290
Test name
Test status
Simulation time 573002533 ps
CPU time 1.34 seconds
Started Jan 21 09:02:32 PM PST 24
Finished Jan 21 09:02:43 PM PST 24
Peak memory 183224 kb
Host smart-bd9798fa-5147-409e-9515-15e58303bc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010825481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.4010825481
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2792264234
Short name T93
Test name
Test status
Simulation time 110643137210 ps
CPU time 62.63 seconds
Started Jan 21 09:02:44 PM PST 24
Finished Jan 21 09:03:51 PM PST 24
Peak memory 183188 kb
Host smart-fd845775-71f8-41ac-a94a-26becc0e27ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792264234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2792264234
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2512965720
Short name T104
Test name
Test status
Simulation time 45601247677 ps
CPU time 152 seconds
Started Jan 21 09:02:33 PM PST 24
Finished Jan 21 09:05:14 PM PST 24
Peak memory 197964 kb
Host smart-d28dde44-145f-45b4-9b87-c25e7ced2a69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512965720 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2512965720
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2514587998
Short name T277
Test name
Test status
Simulation time 565525806 ps
CPU time 0.77 seconds
Started Jan 21 09:02:49 PM PST 24
Finished Jan 21 09:02:54 PM PST 24
Peak memory 183056 kb
Host smart-d2605529-9de7-4309-972f-311601b6a4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514587998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2514587998
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3636561369
Short name T291
Test name
Test status
Simulation time 8972109260 ps
CPU time 14.12 seconds
Started Jan 21 09:02:44 PM PST 24
Finished Jan 21 09:03:03 PM PST 24
Peak memory 183124 kb
Host smart-d6ee196f-7dba-42da-b6ff-4a575cc817c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636561369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3636561369
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2150600330
Short name T294
Test name
Test status
Simulation time 610066269 ps
CPU time 0.79 seconds
Started Jan 21 09:02:45 PM PST 24
Finished Jan 21 09:02:50 PM PST 24
Peak memory 182932 kb
Host smart-49fc8e5e-4aba-4202-947d-9201b0bd1528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150600330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2150600330
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.17877830
Short name T295
Test name
Test status
Simulation time 258106796374 ps
CPU time 341.08 seconds
Started Jan 21 09:02:50 PM PST 24
Finished Jan 21 09:08:35 PM PST 24
Peak memory 183180 kb
Host smart-04b31b6a-a293-4b52-b727-92bfa08397d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17877830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_al
l.17877830
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3533297350
Short name T189
Test name
Test status
Simulation time 115222535353 ps
CPU time 313.7 seconds
Started Jan 21 09:02:44 PM PST 24
Finished Jan 21 09:08:03 PM PST 24
Peak memory 197992 kb
Host smart-4038deb7-c2b6-4886-843a-864ed3ce1a0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533297350 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3533297350
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3930649258
Short name T236
Test name
Test status
Simulation time 607578163 ps
CPU time 0.76 seconds
Started Jan 21 09:02:49 PM PST 24
Finished Jan 21 09:02:54 PM PST 24
Peak memory 183024 kb
Host smart-1d725392-a2b2-4076-a00d-4bdfe2d1b9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930649258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3930649258
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2153237737
Short name T151
Test name
Test status
Simulation time 22523861186 ps
CPU time 18.41 seconds
Started Jan 21 09:02:49 PM PST 24
Finished Jan 21 09:03:12 PM PST 24
Peak memory 183176 kb
Host smart-822a421b-a620-42db-96a7-f3c5037d6c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153237737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2153237737
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1983607246
Short name T156
Test name
Test status
Simulation time 494685426 ps
CPU time 0.72 seconds
Started Jan 21 09:02:47 PM PST 24
Finished Jan 21 09:02:52 PM PST 24
Peak memory 182936 kb
Host smart-1a154916-3014-453f-894d-d7ce8d521772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983607246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1983607246
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1813214534
Short name T90
Test name
Test status
Simulation time 284771518674 ps
CPU time 190.44 seconds
Started Jan 21 09:02:49 PM PST 24
Finished Jan 21 09:06:04 PM PST 24
Peak memory 183048 kb
Host smart-4c1cf098-76ab-41f3-8344-6c1f1d4318ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813214534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1813214534
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2399809588
Short name T249
Test name
Test status
Simulation time 136440647179 ps
CPU time 551.29 seconds
Started Jan 21 09:02:49 PM PST 24
Finished Jan 21 09:12:05 PM PST 24
Peak memory 198020 kb
Host smart-b4e47146-18db-4b1b-b227-ba59656f4051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399809588 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2399809588
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2949686847
Short name T161
Test name
Test status
Simulation time 566959780 ps
CPU time 1.38 seconds
Started Jan 21 09:02:08 PM PST 24
Finished Jan 21 09:02:27 PM PST 24
Peak memory 183012 kb
Host smart-9888f858-328f-459e-b0b1-316a61f01719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949686847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2949686847
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2973794264
Short name T292
Test name
Test status
Simulation time 23449983468 ps
CPU time 16.89 seconds
Started Jan 21 09:02:08 PM PST 24
Finished Jan 21 09:02:42 PM PST 24
Peak memory 183080 kb
Host smart-888a8f22-5caf-44c3-a2f9-2c272e17005a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973794264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2973794264
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1434971301
Short name T33
Test name
Test status
Simulation time 7672581351 ps
CPU time 2.04 seconds
Started Jan 21 09:22:59 PM PST 24
Finished Jan 21 09:23:02 PM PST 24
Peak memory 215328 kb
Host smart-c4d7e6fb-26de-49b9-84d5-53ca798f5add
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434971301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1434971301
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3303111832
Short name T132
Test name
Test status
Simulation time 497452298 ps
CPU time 0.93 seconds
Started Jan 21 09:01:58 PM PST 24
Finished Jan 21 09:02:15 PM PST 24
Peak memory 183060 kb
Host smart-368740ec-5489-457e-8980-be7638b4520e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303111832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3303111832
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.45000714
Short name T209
Test name
Test status
Simulation time 217910673472 ps
CPU time 92.41 seconds
Started Jan 21 09:02:07 PM PST 24
Finished Jan 21 09:03:56 PM PST 24
Peak memory 183140 kb
Host smart-2f1fcf68-ed55-405c-8ded-34d081f95701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45000714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all
.45000714
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3781662782
Short name T139
Test name
Test status
Simulation time 532092436 ps
CPU time 0.97 seconds
Started Jan 21 09:02:49 PM PST 24
Finished Jan 21 09:02:54 PM PST 24
Peak memory 182960 kb
Host smart-2a067076-94a7-414e-889e-d630f9d47e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781662782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3781662782
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3255534127
Short name T125
Test name
Test status
Simulation time 11680539676 ps
CPU time 20.96 seconds
Started Jan 21 09:02:51 PM PST 24
Finished Jan 21 09:03:16 PM PST 24
Peak memory 183136 kb
Host smart-477e4b73-f54c-46e0-9102-16baad794766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255534127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3255534127
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.212752927
Short name T159
Test name
Test status
Simulation time 360087258 ps
CPU time 1.09 seconds
Started Jan 21 09:02:53 PM PST 24
Finished Jan 21 09:02:59 PM PST 24
Peak memory 183100 kb
Host smart-3b60d72f-e6da-4479-b014-ed217cc8d8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212752927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.212752927
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1414013929
Short name T96
Test name
Test status
Simulation time 121745540966 ps
CPU time 46.88 seconds
Started Jan 21 09:02:48 PM PST 24
Finished Jan 21 09:03:40 PM PST 24
Peak memory 193320 kb
Host smart-8255dc3c-47b4-491f-a86f-02c3fa3f1fa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414013929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1414013929
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2126515306
Short name T169
Test name
Test status
Simulation time 72960991414 ps
CPU time 386.14 seconds
Started Jan 21 09:02:42 PM PST 24
Finished Jan 21 09:09:14 PM PST 24
Peak memory 197980 kb
Host smart-48d614d0-066b-42de-b9b7-1750f7be203a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126515306 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2126515306
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.4117750940
Short name T279
Test name
Test status
Simulation time 524419530 ps
CPU time 1.38 seconds
Started Jan 21 09:52:21 PM PST 24
Finished Jan 21 09:52:25 PM PST 24
Peak memory 183068 kb
Host smart-21b92ebd-6162-44b6-9ee8-7814aa2d3d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117750940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.4117750940
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2143989599
Short name T127
Test name
Test status
Simulation time 39137468713 ps
CPU time 57.06 seconds
Started Jan 21 09:02:54 PM PST 24
Finished Jan 21 09:03:57 PM PST 24
Peak memory 183188 kb
Host smart-10a1a9b8-1e63-4700-9405-31a01bd8e4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143989599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2143989599
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3078419654
Short name T122
Test name
Test status
Simulation time 465747834 ps
CPU time 0.73 seconds
Started Jan 21 09:03:02 PM PST 24
Finished Jan 21 09:03:07 PM PST 24
Peak memory 182996 kb
Host smart-65f28e12-3bd3-4ecf-ad9d-d60903f92ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078419654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3078419654
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.645356600
Short name T272
Test name
Test status
Simulation time 327973188735 ps
CPU time 218.01 seconds
Started Jan 21 09:38:08 PM PST 24
Finished Jan 21 09:41:59 PM PST 24
Peak memory 193480 kb
Host smart-a36e9c32-681a-4351-8629-677829b1f37c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645356600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.645356600
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.4050697464
Short name T264
Test name
Test status
Simulation time 80828400069 ps
CPU time 912.04 seconds
Started Jan 21 09:02:52 PM PST 24
Finished Jan 21 09:18:08 PM PST 24
Peak memory 202596 kb
Host smart-df892de6-be21-4bc7-a3f6-345570ea383b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050697464 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.4050697464
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.171006685
Short name T208
Test name
Test status
Simulation time 597529817 ps
CPU time 0.82 seconds
Started Jan 21 11:01:04 PM PST 24
Finished Jan 21 11:01:07 PM PST 24
Peak memory 183144 kb
Host smart-26da7083-1451-4b69-8f40-c65f74b4d8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171006685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.171006685
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.276113738
Short name T40
Test name
Test status
Simulation time 13548272386 ps
CPU time 19.62 seconds
Started Jan 21 09:03:02 PM PST 24
Finished Jan 21 09:03:26 PM PST 24
Peak memory 183176 kb
Host smart-e52cfdfe-ac37-4646-bf77-f112fdc7d925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276113738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.276113738
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1076652371
Short name T186
Test name
Test status
Simulation time 357941077 ps
CPU time 0.67 seconds
Started Jan 21 09:03:02 PM PST 24
Finished Jan 21 09:03:07 PM PST 24
Peak memory 183056 kb
Host smart-3e98b839-916e-494e-96a7-5d0c8cdce356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076652371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1076652371
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.4155265596
Short name T178
Test name
Test status
Simulation time 232607332971 ps
CPU time 80.86 seconds
Started Jan 21 09:21:48 PM PST 24
Finished Jan 21 09:23:16 PM PST 24
Peak memory 193160 kb
Host smart-a8b5105f-6110-42d5-93f3-efa09ab77e1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155265596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.4155265596
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2161055085
Short name T260
Test name
Test status
Simulation time 35093811899 ps
CPU time 313.04 seconds
Started Jan 21 10:00:10 PM PST 24
Finished Jan 21 10:05:33 PM PST 24
Peak memory 198016 kb
Host smart-57e51bf0-f94b-4e9f-9f03-b2aff46f0bb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161055085 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2161055085
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1286710707
Short name T103
Test name
Test status
Simulation time 354365571 ps
CPU time 0.86 seconds
Started Jan 21 09:02:52 PM PST 24
Finished Jan 21 09:02:57 PM PST 24
Peak memory 183232 kb
Host smart-3fbafb3c-40b3-4254-93ef-ef6de0bb12d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286710707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1286710707
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.4240602264
Short name T173
Test name
Test status
Simulation time 59438581722 ps
CPU time 88.59 seconds
Started Jan 21 09:02:52 PM PST 24
Finished Jan 21 09:04:25 PM PST 24
Peak memory 183300 kb
Host smart-10a6d523-5717-4ef2-a5b7-44df06c6c07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240602264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.4240602264
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1875796733
Short name T238
Test name
Test status
Simulation time 491586784 ps
CPU time 1.17 seconds
Started Jan 21 10:54:50 PM PST 24
Finished Jan 21 10:54:53 PM PST 24
Peak memory 183036 kb
Host smart-f32e4944-c0ef-4ca6-a086-9aa5ff1b1ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875796733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1875796733
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.297441611
Short name T22
Test name
Test status
Simulation time 55389310438 ps
CPU time 42.38 seconds
Started Jan 21 09:02:53 PM PST 24
Finished Jan 21 09:03:41 PM PST 24
Peak memory 183188 kb
Host smart-e41b217f-336b-4950-aa4a-848796f8440b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297441611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.297441611
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3035837702
Short name T87
Test name
Test status
Simulation time 580444706 ps
CPU time 0.95 seconds
Started Jan 21 09:02:51 PM PST 24
Finished Jan 21 09:02:57 PM PST 24
Peak memory 183072 kb
Host smart-bd290f9e-3dce-460a-b005-fbe2cd124dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035837702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3035837702
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.557568160
Short name T117
Test name
Test status
Simulation time 41675227366 ps
CPU time 65.64 seconds
Started Jan 21 09:19:39 PM PST 24
Finished Jan 21 09:20:53 PM PST 24
Peak memory 183144 kb
Host smart-ab7365c1-4e56-4cba-ae8f-2970acf6b2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557568160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.557568160
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3309358124
Short name T242
Test name
Test status
Simulation time 603541668 ps
CPU time 0.74 seconds
Started Jan 21 09:02:52 PM PST 24
Finished Jan 21 09:02:57 PM PST 24
Peak memory 183060 kb
Host smart-d191137a-a53b-477e-8a49-d4341852b0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309358124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3309358124
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2019230058
Short name T60
Test name
Test status
Simulation time 167270945339 ps
CPU time 35.85 seconds
Started Jan 21 09:02:53 PM PST 24
Finished Jan 21 09:03:35 PM PST 24
Peak memory 183128 kb
Host smart-4d20742a-3cd5-4528-b813-4748ccd2f3a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019230058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2019230058
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2458820241
Short name T155
Test name
Test status
Simulation time 136517730273 ps
CPU time 119.77 seconds
Started Jan 21 09:03:02 PM PST 24
Finished Jan 21 09:05:06 PM PST 24
Peak memory 197960 kb
Host smart-d61b3748-7438-441d-8ee9-0d3c4ac7278f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458820241 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2458820241
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.79931795
Short name T39
Test name
Test status
Simulation time 584979684 ps
CPU time 0.6 seconds
Started Jan 21 09:02:51 PM PST 24
Finished Jan 21 09:02:56 PM PST 24
Peak memory 183076 kb
Host smart-b493e89a-b941-4b0d-a63f-178530458536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79931795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.79931795
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3327459318
Short name T113
Test name
Test status
Simulation time 5458490351 ps
CPU time 3.05 seconds
Started Jan 21 09:02:51 PM PST 24
Finished Jan 21 09:02:59 PM PST 24
Peak memory 183124 kb
Host smart-82d1c3b0-0971-437d-b829-7ab14a206f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327459318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3327459318
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2806265257
Short name T179
Test name
Test status
Simulation time 591579657 ps
CPU time 0.94 seconds
Started Jan 21 09:02:53 PM PST 24
Finished Jan 21 09:03:00 PM PST 24
Peak memory 182788 kb
Host smart-da6917c9-cbb7-42b3-b5d4-cbd5559e4e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806265257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2806265257
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3447843874
Short name T109
Test name
Test status
Simulation time 31856018996 ps
CPU time 180.79 seconds
Started Jan 21 09:02:51 PM PST 24
Finished Jan 21 09:05:57 PM PST 24
Peak memory 197996 kb
Host smart-23a6471d-e4f3-48f4-a6b5-9d12f49d119a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447843874 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3447843874
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.57011040
Short name T270
Test name
Test status
Simulation time 449708288 ps
CPU time 0.69 seconds
Started Jan 21 09:03:03 PM PST 24
Finished Jan 21 09:03:08 PM PST 24
Peak memory 183024 kb
Host smart-fabdca65-5b29-4a91-ac08-647c4535d4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57011040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.57011040
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.219585399
Short name T229
Test name
Test status
Simulation time 42900899335 ps
CPU time 59.31 seconds
Started Jan 21 09:02:58 PM PST 24
Finished Jan 21 09:04:02 PM PST 24
Peak memory 183104 kb
Host smart-95d403c4-1835-46b0-a543-31b1e4c1c6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219585399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.219585399
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2822161641
Short name T226
Test name
Test status
Simulation time 468131264 ps
CPU time 1.18 seconds
Started Jan 21 09:02:58 PM PST 24
Finished Jan 21 09:03:04 PM PST 24
Peak memory 182936 kb
Host smart-c03fc03d-5c1d-4eb2-80ff-12a0534fd3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822161641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2822161641
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.924996347
Short name T289
Test name
Test status
Simulation time 126388582466 ps
CPU time 171.38 seconds
Started Jan 21 09:03:03 PM PST 24
Finished Jan 21 09:05:59 PM PST 24
Peak memory 183136 kb
Host smart-0be54448-ca54-4ffd-afcc-f25814ff2d61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924996347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.924996347
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.4289841061
Short name T88
Test name
Test status
Simulation time 49016761452 ps
CPU time 466.93 seconds
Started Jan 21 09:03:02 PM PST 24
Finished Jan 21 09:10:53 PM PST 24
Peak memory 197988 kb
Host smart-0e1901c9-487f-4bae-8ed9-02a1af0e1a03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289841061 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.4289841061
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2422899180
Short name T41
Test name
Test status
Simulation time 493441856 ps
CPU time 0.93 seconds
Started Jan 21 09:02:58 PM PST 24
Finished Jan 21 09:03:04 PM PST 24
Peak memory 183036 kb
Host smart-904c91c5-77e2-42ff-b3b0-0cccd3b0e399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422899180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2422899180
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3918245487
Short name T34
Test name
Test status
Simulation time 41320216417 ps
CPU time 16.33 seconds
Started Jan 21 09:02:57 PM PST 24
Finished Jan 21 09:03:18 PM PST 24
Peak memory 183348 kb
Host smart-27c1c6f1-0dd6-482a-969f-919cac81e8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918245487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3918245487
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.293760149
Short name T129
Test name
Test status
Simulation time 514639207 ps
CPU time 0.99 seconds
Started Jan 21 09:02:59 PM PST 24
Finished Jan 21 09:03:05 PM PST 24
Peak memory 182896 kb
Host smart-6e523865-c9be-4718-b1d9-c5084f0312ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293760149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.293760149
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3274181593
Short name T114
Test name
Test status
Simulation time 211299867332 ps
CPU time 158.7 seconds
Started Jan 21 09:02:57 PM PST 24
Finished Jan 21 09:05:41 PM PST 24
Peak memory 183184 kb
Host smart-c71738d9-79f4-4b02-94d4-123d36eae71c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274181593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3274181593
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.4018580377
Short name T54
Test name
Test status
Simulation time 95369365585 ps
CPU time 280.61 seconds
Started Jan 21 09:03:03 PM PST 24
Finished Jan 21 09:07:48 PM PST 24
Peak memory 197936 kb
Host smart-9425dd98-daa0-494e-9039-18f79ba7a6f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018580377 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.4018580377
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.551193364
Short name T176
Test name
Test status
Simulation time 438406430 ps
CPU time 0.88 seconds
Started Jan 21 09:03:00 PM PST 24
Finished Jan 21 09:03:06 PM PST 24
Peak memory 183076 kb
Host smart-5c382fa2-9be9-42f2-82c0-be54b76d6c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551193364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.551193364
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.462694520
Short name T158
Test name
Test status
Simulation time 10314313795 ps
CPU time 17.12 seconds
Started Jan 21 09:02:58 PM PST 24
Finished Jan 21 09:03:20 PM PST 24
Peak memory 183124 kb
Host smart-05da8035-4506-49d5-964d-981850b1ffab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462694520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.462694520
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1150985096
Short name T219
Test name
Test status
Simulation time 603440446 ps
CPU time 0.62 seconds
Started Jan 21 09:02:56 PM PST 24
Finished Jan 21 09:03:03 PM PST 24
Peak memory 182936 kb
Host smart-fa0f148f-36f6-4e56-9fd0-6e12bec01649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150985096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1150985096
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3781071003
Short name T215
Test name
Test status
Simulation time 412622327026 ps
CPU time 447.67 seconds
Started Jan 21 09:02:58 PM PST 24
Finished Jan 21 09:10:30 PM PST 24
Peak memory 194284 kb
Host smart-0c7b502b-a7b1-489f-ac7e-83bc7bf1f3d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781071003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3781071003
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3557602918
Short name T297
Test name
Test status
Simulation time 128783583413 ps
CPU time 367.8 seconds
Started Jan 21 09:03:00 PM PST 24
Finished Jan 21 09:09:13 PM PST 24
Peak memory 198048 kb
Host smart-7a522dc8-4af1-45bd-9da7-b8d20f133dfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557602918 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3557602918
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.4050098713
Short name T143
Test name
Test status
Simulation time 473251485 ps
CPU time 1.28 seconds
Started Jan 21 09:03:00 PM PST 24
Finished Jan 21 09:03:05 PM PST 24
Peak memory 183060 kb
Host smart-5d0efc63-bc71-4237-a4fd-82139f16a1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050098713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.4050098713
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.34761494
Short name T146
Test name
Test status
Simulation time 31271144088 ps
CPU time 51.87 seconds
Started Jan 21 09:03:00 PM PST 24
Finished Jan 21 09:03:57 PM PST 24
Peak memory 183148 kb
Host smart-2477c02d-da51-4268-90a6-4c366a493239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34761494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.34761494
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.839644950
Short name T142
Test name
Test status
Simulation time 594654107 ps
CPU time 1.04 seconds
Started Jan 21 09:02:56 PM PST 24
Finished Jan 21 09:03:03 PM PST 24
Peak memory 182828 kb
Host smart-7eb32891-cc8c-4588-ab29-5342bc9f297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839644950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.839644950
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1325391631
Short name T265
Test name
Test status
Simulation time 169408133586 ps
CPU time 61.66 seconds
Started Jan 21 09:02:56 PM PST 24
Finished Jan 21 09:04:04 PM PST 24
Peak memory 194556 kb
Host smart-a35a6d25-04f5-4d32-82b0-00e3499d35c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325391631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1325391631
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.620202988
Short name T237
Test name
Test status
Simulation time 150197339520 ps
CPU time 581.84 seconds
Started Jan 21 09:03:00 PM PST 24
Finished Jan 21 09:12:46 PM PST 24
Peak memory 206204 kb
Host smart-5eca6b46-47cb-4f52-814e-58358694ec3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620202988 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.620202988
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2053349606
Short name T254
Test name
Test status
Simulation time 631581175 ps
CPU time 1.01 seconds
Started Jan 21 09:01:59 PM PST 24
Finished Jan 21 09:02:17 PM PST 24
Peak memory 183024 kb
Host smart-9d681286-4bcd-425a-b2f7-529a594e3bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053349606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2053349606
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.4032361241
Short name T116
Test name
Test status
Simulation time 28543934495 ps
CPU time 21.71 seconds
Started Jan 21 09:02:00 PM PST 24
Finished Jan 21 09:02:38 PM PST 24
Peak memory 183200 kb
Host smart-11026f77-0d3b-4612-9dd4-ca146b6685fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032361241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.4032361241
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.954510389
Short name T29
Test name
Test status
Simulation time 7546965797 ps
CPU time 12.43 seconds
Started Jan 21 09:01:58 PM PST 24
Finished Jan 21 09:02:27 PM PST 24
Peak memory 215396 kb
Host smart-1beb4c76-1f8f-4f2d-8ce0-81786906f70c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954510389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.954510389
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.353923056
Short name T133
Test name
Test status
Simulation time 409461611 ps
CPU time 0.7 seconds
Started Jan 21 09:02:00 PM PST 24
Finished Jan 21 09:02:17 PM PST 24
Peak memory 182952 kb
Host smart-8c92ecc7-de0c-48a9-bb95-7cb4b2ea0149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353923056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.353923056
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3681284514
Short name T85
Test name
Test status
Simulation time 83282431827 ps
CPU time 31.13 seconds
Started Jan 21 09:02:04 PM PST 24
Finished Jan 21 09:02:51 PM PST 24
Peak memory 183352 kb
Host smart-95ea04c6-a67d-455e-99ab-c6b912ee99eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681284514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3681284514
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2383115330
Short name T95
Test name
Test status
Simulation time 21831778814 ps
CPU time 205.59 seconds
Started Jan 21 10:07:28 PM PST 24
Finished Jan 21 10:10:55 PM PST 24
Peak memory 198028 kb
Host smart-5eab2a77-47ee-43a8-8a75-6ec4919fe11e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383115330 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2383115330
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2653585008
Short name T246
Test name
Test status
Simulation time 420960183 ps
CPU time 1.19 seconds
Started Jan 21 09:03:08 PM PST 24
Finished Jan 21 09:03:14 PM PST 24
Peak memory 183024 kb
Host smart-c0a6b014-06fe-42d4-890a-21731f64effb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653585008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2653585008
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3279984351
Short name T153
Test name
Test status
Simulation time 17522610812 ps
CPU time 3.62 seconds
Started Jan 21 09:03:09 PM PST 24
Finished Jan 21 09:03:20 PM PST 24
Peak memory 183124 kb
Host smart-dccb5ef6-5eb0-45ae-b256-134367177a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279984351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3279984351
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1958510799
Short name T141
Test name
Test status
Simulation time 523378320 ps
CPU time 1.23 seconds
Started Jan 21 09:03:08 PM PST 24
Finished Jan 21 09:03:14 PM PST 24
Peak memory 183076 kb
Host smart-851320da-72f6-4bf9-9eb3-7e02ec70d1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958510799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1958510799
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1084327207
Short name T157
Test name
Test status
Simulation time 111503836985 ps
CPU time 157.76 seconds
Started Jan 21 09:03:09 PM PST 24
Finished Jan 21 09:05:55 PM PST 24
Peak memory 183192 kb
Host smart-6241f66a-b706-4165-be58-18346719fc00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084327207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1084327207
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.444209757
Short name T37
Test name
Test status
Simulation time 183029301892 ps
CPU time 389.79 seconds
Started Jan 21 09:03:07 PM PST 24
Finished Jan 21 09:09:41 PM PST 24
Peak memory 198012 kb
Host smart-e26709aa-e65e-4957-828c-93c17114cac7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444209757 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.444209757
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3181124084
Short name T200
Test name
Test status
Simulation time 557424652 ps
CPU time 0.67 seconds
Started Jan 21 09:03:04 PM PST 24
Finished Jan 21 09:03:09 PM PST 24
Peak memory 183024 kb
Host smart-6cf035f4-68d6-4eba-8541-1160ece91ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181124084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3181124084
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.755593867
Short name T266
Test name
Test status
Simulation time 28561856083 ps
CPU time 36.11 seconds
Started Jan 21 09:03:05 PM PST 24
Finished Jan 21 09:03:46 PM PST 24
Peak memory 183140 kb
Host smart-30225543-6482-4a5f-8755-dfa54d2b0c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755593867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.755593867
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2929071779
Short name T138
Test name
Test status
Simulation time 357666593 ps
CPU time 1.12 seconds
Started Jan 21 09:03:08 PM PST 24
Finished Jan 21 09:03:14 PM PST 24
Peak memory 182892 kb
Host smart-18ec82d5-34a0-4c01-9323-a8c76dac4772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929071779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2929071779
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.4100928902
Short name T227
Test name
Test status
Simulation time 198308866438 ps
CPU time 229.1 seconds
Started Jan 21 09:03:10 PM PST 24
Finished Jan 21 09:07:08 PM PST 24
Peak memory 183176 kb
Host smart-36963b93-d134-4d78-bd51-27a5fa12be7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100928902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.4100928902
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2237309963
Short name T232
Test name
Test status
Simulation time 59884051089 ps
CPU time 674.59 seconds
Started Jan 21 09:03:09 PM PST 24
Finished Jan 21 09:14:32 PM PST 24
Peak memory 206616 kb
Host smart-ea262ca7-731f-4451-b1ba-ce8ccd60eb7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237309963 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2237309963
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1802615360
Short name T136
Test name
Test status
Simulation time 624462180 ps
CPU time 0.74 seconds
Started Jan 21 09:03:16 PM PST 24
Finished Jan 21 09:03:29 PM PST 24
Peak memory 183016 kb
Host smart-5003aeba-556e-4949-84d8-9c73acc25125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802615360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1802615360
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2668268499
Short name T121
Test name
Test status
Simulation time 18970087713 ps
CPU time 7.05 seconds
Started Jan 21 09:03:10 PM PST 24
Finished Jan 21 09:03:26 PM PST 24
Peak memory 183140 kb
Host smart-a011d932-8983-4a16-b41d-d4a9aa90c707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668268499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2668268499
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3960550289
Short name T284
Test name
Test status
Simulation time 377779404 ps
CPU time 0.86 seconds
Started Jan 21 09:03:05 PM PST 24
Finished Jan 21 09:03:10 PM PST 24
Peak memory 182932 kb
Host smart-fcccca0f-d123-4bde-bf47-d7d283cbd6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960550289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3960550289
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3081726409
Short name T124
Test name
Test status
Simulation time 170921643551 ps
CPU time 63.5 seconds
Started Jan 21 09:03:16 PM PST 24
Finished Jan 21 09:04:32 PM PST 24
Peak memory 193304 kb
Host smart-6ffb2aa0-418f-441a-85df-597d2d7b46fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081726409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3081726409
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.4082252116
Short name T244
Test name
Test status
Simulation time 176711083379 ps
CPU time 317.45 seconds
Started Jan 21 09:03:18 PM PST 24
Finished Jan 21 09:08:47 PM PST 24
Peak memory 197952 kb
Host smart-1e80e252-2f6a-4dc9-a743-7f6486654fb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082252116 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.4082252116
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.4020664798
Short name T21
Test name
Test status
Simulation time 627091790 ps
CPU time 0.7 seconds
Started Jan 21 09:03:19 PM PST 24
Finished Jan 21 09:03:33 PM PST 24
Peak memory 183024 kb
Host smart-5de1e06f-703e-47a5-b248-f348e35d001b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020664798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.4020664798
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.974443388
Short name T123
Test name
Test status
Simulation time 9884836263 ps
CPU time 7.3 seconds
Started Jan 21 09:03:15 PM PST 24
Finished Jan 21 09:03:35 PM PST 24
Peak memory 183176 kb
Host smart-a032a43d-8168-4380-b0e2-26e3384a8f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974443388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.974443388
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2688617067
Short name T212
Test name
Test status
Simulation time 478959338 ps
CPU time 1.28 seconds
Started Jan 21 09:03:15 PM PST 24
Finished Jan 21 09:03:29 PM PST 24
Peak memory 182920 kb
Host smart-5c47b139-7bc9-49d3-8ce3-3f60e058d7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688617067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2688617067
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3517638018
Short name T188
Test name
Test status
Simulation time 281082644086 ps
CPU time 463.72 seconds
Started Jan 21 09:03:22 PM PST 24
Finished Jan 21 09:11:21 PM PST 24
Peak memory 183148 kb
Host smart-fadd702f-31df-4051-8e8f-56e507f2bd7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517638018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3517638018
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1207060990
Short name T19
Test name
Test status
Simulation time 533715300457 ps
CPU time 181.51 seconds
Started Jan 21 09:03:13 PM PST 24
Finished Jan 21 09:06:29 PM PST 24
Peak memory 197992 kb
Host smart-b903b7ea-dd23-4a87-be42-db0f5e168c95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207060990 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1207060990
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1737894814
Short name T216
Test name
Test status
Simulation time 588751302 ps
CPU time 1.37 seconds
Started Jan 21 09:03:15 PM PST 24
Finished Jan 21 09:03:29 PM PST 24
Peak memory 183000 kb
Host smart-a7ed6763-57f1-444f-9f68-cdf7e790c3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737894814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1737894814
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.315706293
Short name T187
Test name
Test status
Simulation time 25565905057 ps
CPU time 38 seconds
Started Jan 21 09:03:18 PM PST 24
Finished Jan 21 09:04:07 PM PST 24
Peak memory 183176 kb
Host smart-c058fad1-6c75-420b-a3d8-0e558b145393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315706293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.315706293
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1774292654
Short name T267
Test name
Test status
Simulation time 523213887 ps
CPU time 1.1 seconds
Started Jan 21 09:03:20 PM PST 24
Finished Jan 21 09:03:36 PM PST 24
Peak memory 182936 kb
Host smart-0d2e304e-fea2-4929-9c1f-64012f966abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774292654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1774292654
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3959521197
Short name T261
Test name
Test status
Simulation time 97381722406 ps
CPU time 35.12 seconds
Started Jan 21 09:03:19 PM PST 24
Finished Jan 21 09:04:07 PM PST 24
Peak memory 183128 kb
Host smart-5247f03e-1dfc-4f15-807e-5525355030ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959521197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3959521197
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3678088651
Short name T62
Test name
Test status
Simulation time 307899034083 ps
CPU time 559.09 seconds
Started Jan 21 09:03:20 PM PST 24
Finished Jan 21 09:12:54 PM PST 24
Peak memory 198044 kb
Host smart-19d3cd43-9f8d-4f33-adc0-3ef6e8519323
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678088651 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3678088651
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2555991356
Short name T196
Test name
Test status
Simulation time 457455489 ps
CPU time 0.69 seconds
Started Jan 21 09:03:24 PM PST 24
Finished Jan 21 09:03:42 PM PST 24
Peak memory 183020 kb
Host smart-a780f18d-51de-4732-a99f-91ad1aa63dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555991356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2555991356
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3499434795
Short name T231
Test name
Test status
Simulation time 56988799622 ps
CPU time 80.32 seconds
Started Jan 21 09:03:25 PM PST 24
Finished Jan 21 09:05:03 PM PST 24
Peak memory 183200 kb
Host smart-eecc59af-ce61-4c42-b276-f1543bbc8495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499434795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3499434795
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1526889449
Short name T221
Test name
Test status
Simulation time 568478694 ps
CPU time 1.42 seconds
Started Jan 21 10:23:12 PM PST 24
Finished Jan 21 10:23:17 PM PST 24
Peak memory 183060 kb
Host smart-3610183a-abdd-4980-b794-0e75333edb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526889449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1526889449
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.34769271
Short name T84
Test name
Test status
Simulation time 11054371617 ps
CPU time 8.87 seconds
Started Jan 21 09:28:27 PM PST 24
Finished Jan 21 09:28:43 PM PST 24
Peak memory 194628 kb
Host smart-bbcb8a53-a3b8-4c9c-a481-2954f7e966c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34769271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_al
l.34769271
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2161126258
Short name T145
Test name
Test status
Simulation time 500839334 ps
CPU time 0.95 seconds
Started Jan 21 09:43:10 PM PST 24
Finished Jan 21 09:43:12 PM PST 24
Peak memory 183060 kb
Host smart-c50b9c4a-efca-4001-968c-12f2808ce2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161126258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2161126258
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3485888379
Short name T210
Test name
Test status
Simulation time 38433276995 ps
CPU time 58.81 seconds
Started Jan 21 09:03:26 PM PST 24
Finished Jan 21 09:04:42 PM PST 24
Peak memory 183128 kb
Host smart-21b4cd96-fc21-4c2b-94ee-7058a9c5ba23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485888379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3485888379
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1126677414
Short name T193
Test name
Test status
Simulation time 560777579 ps
CPU time 1.39 seconds
Started Jan 21 09:03:26 PM PST 24
Finished Jan 21 09:03:45 PM PST 24
Peak memory 182952 kb
Host smart-69ecb5bf-a2a1-4b37-b3f2-f4924a394b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126677414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1126677414
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.557646374
Short name T228
Test name
Test status
Simulation time 790024243462 ps
CPU time 319.32 seconds
Started Jan 21 09:23:13 PM PST 24
Finished Jan 21 09:28:42 PM PST 24
Peak memory 183172 kb
Host smart-f6147549-0d69-4d36-a4be-fc999ecceeb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557646374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.557646374
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2431983304
Short name T213
Test name
Test status
Simulation time 349501571525 ps
CPU time 709.24 seconds
Started Jan 21 09:03:25 PM PST 24
Finished Jan 21 09:15:32 PM PST 24
Peak memory 199548 kb
Host smart-f3d4f99e-d586-43bb-90ac-bae916a67f15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431983304 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2431983304
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3479979954
Short name T276
Test name
Test status
Simulation time 346473552 ps
CPU time 1.1 seconds
Started Jan 21 09:03:24 PM PST 24
Finished Jan 21 09:03:42 PM PST 24
Peak memory 183048 kb
Host smart-4dd2f1fe-e071-4b61-8b95-d030ce14070a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479979954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3479979954
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3414585702
Short name T149
Test name
Test status
Simulation time 1317762431 ps
CPU time 1.05 seconds
Started Jan 21 09:03:25 PM PST 24
Finished Jan 21 09:03:43 PM PST 24
Peak memory 182888 kb
Host smart-c105f5ef-650b-4c1d-9222-31f905fd35f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414585702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3414585702
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3993915747
Short name T154
Test name
Test status
Simulation time 511545766 ps
CPU time 1.2 seconds
Started Jan 21 09:03:25 PM PST 24
Finished Jan 21 09:03:44 PM PST 24
Peak memory 182944 kb
Host smart-78c08d01-c683-494d-819c-e9b1ffb077ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993915747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3993915747
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.372147510
Short name T110
Test name
Test status
Simulation time 240213462376 ps
CPU time 387.67 seconds
Started Jan 21 09:27:26 PM PST 24
Finished Jan 21 09:33:55 PM PST 24
Peak memory 193152 kb
Host smart-e5fd773f-5f75-4e7c-9791-85c4d222dcf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372147510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.372147510
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.307140862
Short name T63
Test name
Test status
Simulation time 425672715230 ps
CPU time 986.81 seconds
Started Jan 21 10:30:23 PM PST 24
Finished Jan 21 10:47:04 PM PST 24
Peak memory 203916 kb
Host smart-525f2372-0fca-40e4-ba8e-210c5385a821
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307140862 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.307140862
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2844033069
Short name T134
Test name
Test status
Simulation time 479226614 ps
CPU time 0.72 seconds
Started Jan 21 09:03:31 PM PST 24
Finished Jan 21 09:03:48 PM PST 24
Peak memory 183004 kb
Host smart-7e6a9daa-62f4-4227-9720-acb5554e3452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844033069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2844033069
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1427729355
Short name T182
Test name
Test status
Simulation time 45637104137 ps
CPU time 67.74 seconds
Started Jan 21 09:03:34 PM PST 24
Finished Jan 21 09:04:57 PM PST 24
Peak memory 183120 kb
Host smart-641025d3-cf07-44a8-9011-352cb7aef254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427729355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1427729355
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3060791269
Short name T201
Test name
Test status
Simulation time 390106669 ps
CPU time 1.13 seconds
Started Jan 21 09:03:32 PM PST 24
Finished Jan 21 09:03:49 PM PST 24
Peak memory 182936 kb
Host smart-59a0eb7b-e4e2-4f8b-83a4-b9fe8f1c94ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060791269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3060791269
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1680178239
Short name T102
Test name
Test status
Simulation time 8321615549 ps
CPU time 3.74 seconds
Started Jan 21 09:03:31 PM PST 24
Finished Jan 21 09:03:51 PM PST 24
Peak memory 183188 kb
Host smart-4f4ac56e-40f7-4756-a6b7-76117243456e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680178239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1680178239
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.528505004
Short name T248
Test name
Test status
Simulation time 39286486219 ps
CPU time 299.67 seconds
Started Jan 21 09:43:08 PM PST 24
Finished Jan 21 09:48:09 PM PST 24
Peak memory 197976 kb
Host smart-86d63411-bbf4-4174-9aeb-806a164d2670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528505004 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.528505004
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2879480904
Short name T223
Test name
Test status
Simulation time 445732142 ps
CPU time 0.74 seconds
Started Jan 21 09:59:12 PM PST 24
Finished Jan 21 09:59:14 PM PST 24
Peak memory 183024 kb
Host smart-2b20cb4d-3788-4974-b8f5-11cb11ce41da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879480904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2879480904
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.657924731
Short name T185
Test name
Test status
Simulation time 33984672795 ps
CPU time 14.05 seconds
Started Jan 21 09:18:20 PM PST 24
Finished Jan 21 09:18:38 PM PST 24
Peak memory 183144 kb
Host smart-27878a15-b5f3-4075-a3d6-2e8afc48a22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657924731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.657924731
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3002840118
Short name T194
Test name
Test status
Simulation time 434877612 ps
CPU time 0.8 seconds
Started Jan 21 09:59:37 PM PST 24
Finished Jan 21 09:59:44 PM PST 24
Peak memory 183020 kb
Host smart-68f32041-a054-4fb8-92aa-dc72b32a4101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002840118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3002840118
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2604928774
Short name T233
Test name
Test status
Simulation time 121282807661 ps
CPU time 25.75 seconds
Started Jan 21 09:03:31 PM PST 24
Finished Jan 21 09:04:13 PM PST 24
Peak memory 183188 kb
Host smart-0ab98fdb-41d6-4877-8072-649a1c874ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604928774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2604928774
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2603606760
Short name T288
Test name
Test status
Simulation time 50398083248 ps
CPU time 410.25 seconds
Started Jan 21 10:48:02 PM PST 24
Finished Jan 21 10:54:57 PM PST 24
Peak memory 197968 kb
Host smart-1f09a628-5ba1-4210-849b-1e3bd60576c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603606760 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2603606760
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1109963251
Short name T230
Test name
Test status
Simulation time 361954246 ps
CPU time 0.82 seconds
Started Jan 21 09:02:08 PM PST 24
Finished Jan 21 09:02:26 PM PST 24
Peak memory 182992 kb
Host smart-ffa56dcb-3cc3-4c16-a887-12c9731d27b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109963251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1109963251
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2221045831
Short name T135
Test name
Test status
Simulation time 39029309773 ps
CPU time 15.04 seconds
Started Jan 21 09:02:00 PM PST 24
Finished Jan 21 09:02:31 PM PST 24
Peak memory 183188 kb
Host smart-1ff46df2-a6da-4ecf-bb75-cd9208b4bca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221045831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2221045831
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2529458980
Short name T30
Test name
Test status
Simulation time 4245123742 ps
CPU time 7.03 seconds
Started Jan 21 09:01:58 PM PST 24
Finished Jan 21 09:02:21 PM PST 24
Peak memory 215028 kb
Host smart-e70ce3a2-7c3a-4a18-a7e8-7950a9b977ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529458980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2529458980
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3252933252
Short name T268
Test name
Test status
Simulation time 538691371 ps
CPU time 0.97 seconds
Started Jan 21 09:01:59 PM PST 24
Finished Jan 21 09:02:17 PM PST 24
Peak memory 183036 kb
Host smart-c335bc88-e0b9-43ad-9cfd-55e3956d0c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252933252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3252933252
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1855961108
Short name T271
Test name
Test status
Simulation time 318386093120 ps
CPU time 485.81 seconds
Started Jan 21 09:02:04 PM PST 24
Finished Jan 21 09:10:25 PM PST 24
Peak memory 191552 kb
Host smart-a9ba2bc6-7799-4f14-b149-3b326a0a67c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855961108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1855961108
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2071960718
Short name T150
Test name
Test status
Simulation time 37794519812 ps
CPU time 142.67 seconds
Started Jan 21 09:02:00 PM PST 24
Finished Jan 21 09:04:39 PM PST 24
Peak memory 197992 kb
Host smart-fec15332-f64c-427f-90a3-fd1d124123f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071960718 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2071960718
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1065122753
Short name T247
Test name
Test status
Simulation time 581352548 ps
CPU time 0.74 seconds
Started Jan 21 09:03:31 PM PST 24
Finished Jan 21 09:03:48 PM PST 24
Peak memory 183072 kb
Host smart-db889659-3cd4-43cd-8b04-c913850caab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065122753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1065122753
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.965299369
Short name T211
Test name
Test status
Simulation time 26779120663 ps
CPU time 10.87 seconds
Started Jan 21 09:03:33 PM PST 24
Finished Jan 21 09:03:59 PM PST 24
Peak memory 183124 kb
Host smart-531479f6-7bef-4610-a905-76f7fe8a2933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965299369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.965299369
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2295204484
Short name T120
Test name
Test status
Simulation time 377654545 ps
CPU time 0.83 seconds
Started Jan 21 10:05:59 PM PST 24
Finished Jan 21 10:06:05 PM PST 24
Peak memory 182936 kb
Host smart-92ba9933-4084-4fb8-a309-cecc6a36f54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295204484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2295204484
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1066623821
Short name T165
Test name
Test status
Simulation time 40582562224 ps
CPU time 9 seconds
Started Jan 21 09:04:07 PM PST 24
Finished Jan 21 09:04:19 PM PST 24
Peak memory 193552 kb
Host smart-f63c890a-d8e7-46e5-8b36-1b8313224d79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066623821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1066623821
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.4147293000
Short name T239
Test name
Test status
Simulation time 41586178373 ps
CPU time 295.82 seconds
Started Jan 21 10:55:50 PM PST 24
Finished Jan 21 11:00:47 PM PST 24
Peak memory 197988 kb
Host smart-8e0ca894-d360-48ca-a78c-7aa092a0cd7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147293000 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.4147293000
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.484774268
Short name T111
Test name
Test status
Simulation time 484772578 ps
CPU time 0.61 seconds
Started Jan 21 09:04:09 PM PST 24
Finished Jan 21 09:04:11 PM PST 24
Peak memory 183004 kb
Host smart-2ee01e60-2cc0-4ea6-8dbd-21e751f96fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484774268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.484774268
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3657890019
Short name T162
Test name
Test status
Simulation time 8273985708 ps
CPU time 3.8 seconds
Started Jan 21 09:04:07 PM PST 24
Finished Jan 21 09:04:14 PM PST 24
Peak memory 183136 kb
Host smart-f7684250-20af-4004-a118-dfcf25b688f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657890019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3657890019
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3900392959
Short name T234
Test name
Test status
Simulation time 537446357 ps
CPU time 0.75 seconds
Started Jan 21 09:04:12 PM PST 24
Finished Jan 21 09:04:14 PM PST 24
Peak memory 183056 kb
Host smart-45676741-76fe-44d4-8170-752b6506b350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900392959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3900392959
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.579641486
Short name T105
Test name
Test status
Simulation time 242847916328 ps
CPU time 191.36 seconds
Started Jan 21 09:04:06 PM PST 24
Finished Jan 21 09:07:21 PM PST 24
Peak memory 183128 kb
Host smart-03b2f4d2-ebf8-43c8-8e69-1a71d445b09d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579641486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.579641486
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3003635415
Short name T53
Test name
Test status
Simulation time 31144750952 ps
CPU time 269.14 seconds
Started Jan 21 09:04:09 PM PST 24
Finished Jan 21 09:08:40 PM PST 24
Peak memory 197956 kb
Host smart-3794633a-0580-45a1-afe4-49cc63d3b5f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003635415 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3003635415
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1315786036
Short name T167
Test name
Test status
Simulation time 480527624 ps
CPU time 0.75 seconds
Started Jan 21 09:04:17 PM PST 24
Finished Jan 21 09:04:28 PM PST 24
Peak memory 183048 kb
Host smart-18599e0a-9577-4c55-8d70-8d0488ab5dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315786036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1315786036
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3714696459
Short name T198
Test name
Test status
Simulation time 24733830129 ps
CPU time 38.62 seconds
Started Jan 21 09:04:07 PM PST 24
Finished Jan 21 09:04:48 PM PST 24
Peak memory 183176 kb
Host smart-16b585c9-f289-4551-9251-bea6dedfa487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714696459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3714696459
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1410069781
Short name T164
Test name
Test status
Simulation time 424072224 ps
CPU time 0.72 seconds
Started Jan 21 09:04:11 PM PST 24
Finished Jan 21 09:04:13 PM PST 24
Peak memory 182932 kb
Host smart-882fba96-6095-4a65-a628-659df305e389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410069781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1410069781
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2754790798
Short name T24
Test name
Test status
Simulation time 190858330538 ps
CPU time 22.46 seconds
Started Jan 21 09:04:15 PM PST 24
Finished Jan 21 09:04:47 PM PST 24
Peak memory 183132 kb
Host smart-50fb7ae4-b18a-46c6-9d2a-671b441c3bd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754790798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2754790798
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3506195618
Short name T207
Test name
Test status
Simulation time 128636972743 ps
CPU time 187.95 seconds
Started Jan 21 09:04:23 PM PST 24
Finished Jan 21 09:07:37 PM PST 24
Peak memory 197980 kb
Host smart-2b84fd46-4e60-4051-9e78-56a18693db22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506195618 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3506195618
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2506561764
Short name T192
Test name
Test status
Simulation time 433038851 ps
CPU time 0.72 seconds
Started Jan 21 09:04:23 PM PST 24
Finished Jan 21 09:04:30 PM PST 24
Peak memory 183016 kb
Host smart-7a766ecd-322a-4dc9-953a-ed3cb8712c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506561764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2506561764
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.878020096
Short name T147
Test name
Test status
Simulation time 31940149777 ps
CPU time 11.38 seconds
Started Jan 21 09:04:16 PM PST 24
Finished Jan 21 09:04:37 PM PST 24
Peak memory 183124 kb
Host smart-4addac0c-62ec-4118-9c76-b2c942a1f2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878020096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.878020096
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.121408228
Short name T274
Test name
Test status
Simulation time 426613527 ps
CPU time 1.21 seconds
Started Jan 21 09:04:22 PM PST 24
Finished Jan 21 09:04:30 PM PST 24
Peak memory 182880 kb
Host smart-d390d2a3-61df-4c7e-aa67-95f37a74dbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121408228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.121408228
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.4268303193
Short name T287
Test name
Test status
Simulation time 24115088424 ps
CPU time 8.96 seconds
Started Jan 21 09:04:29 PM PST 24
Finished Jan 21 09:04:46 PM PST 24
Peak memory 193060 kb
Host smart-697f0e66-5347-4361-8880-14c32ead4d7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268303193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.4268303193
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3888528478
Short name T243
Test name
Test status
Simulation time 57258987756 ps
CPU time 369.43 seconds
Started Jan 21 09:04:14 PM PST 24
Finished Jan 21 09:10:25 PM PST 24
Peak memory 197996 kb
Host smart-25bba655-9151-4b1d-b2c0-7aee43f37e02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888528478 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3888528478
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3211150743
Short name T144
Test name
Test status
Simulation time 399732838 ps
CPU time 0.69 seconds
Started Jan 21 09:04:24 PM PST 24
Finished Jan 21 09:04:30 PM PST 24
Peak memory 183004 kb
Host smart-f663f51a-e60c-4205-b29a-32fcd9fd0d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211150743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3211150743
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1623261400
Short name T205
Test name
Test status
Simulation time 53256367031 ps
CPU time 20.61 seconds
Started Jan 21 09:27:27 PM PST 24
Finished Jan 21 09:27:49 PM PST 24
Peak memory 183148 kb
Host smart-7026193b-8aa9-4f04-a9c4-cfed303041e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623261400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1623261400
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3495040494
Short name T51
Test name
Test status
Simulation time 619867222 ps
CPU time 0.69 seconds
Started Jan 21 09:04:24 PM PST 24
Finished Jan 21 09:04:30 PM PST 24
Peak memory 183028 kb
Host smart-83a5fdaa-9782-4bca-b4f7-6ffe56361d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495040494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3495040494
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3116534958
Short name T252
Test name
Test status
Simulation time 150810087251 ps
CPU time 54.26 seconds
Started Jan 21 09:04:24 PM PST 24
Finished Jan 21 09:05:24 PM PST 24
Peak memory 183352 kb
Host smart-3f3cd0c7-e117-4c0e-bd89-1a1e0a3551ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116534958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3116534958
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2870919538
Short name T89
Test name
Test status
Simulation time 143137043645 ps
CPU time 969.48 seconds
Started Jan 21 09:04:24 PM PST 24
Finished Jan 21 09:20:39 PM PST 24
Peak memory 200736 kb
Host smart-dc825266-389e-4ae2-a0e8-cb364c25d6c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870919538 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2870919538
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1898589154
Short name T108
Test name
Test status
Simulation time 583802900 ps
CPU time 0.73 seconds
Started Jan 21 09:04:28 PM PST 24
Finished Jan 21 09:04:37 PM PST 24
Peak memory 183012 kb
Host smart-e4f0839d-7726-4166-ba5b-e5567935353f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898589154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1898589154
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1132320771
Short name T206
Test name
Test status
Simulation time 26613043392 ps
CPU time 3.99 seconds
Started Jan 21 09:04:26 PM PST 24
Finished Jan 21 09:04:39 PM PST 24
Peak memory 183136 kb
Host smart-318970df-c194-4547-ada2-c196b95ad0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132320771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1132320771
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2038505629
Short name T241
Test name
Test status
Simulation time 453440138 ps
CPU time 0.75 seconds
Started Jan 21 09:04:30 PM PST 24
Finished Jan 21 09:04:38 PM PST 24
Peak memory 182896 kb
Host smart-a1ab2cec-d50a-4fe1-8c3e-57bbc6a6d582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038505629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2038505629
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3110282540
Short name T218
Test name
Test status
Simulation time 271723760416 ps
CPU time 412.29 seconds
Started Jan 21 09:04:21 PM PST 24
Finished Jan 21 09:11:21 PM PST 24
Peak memory 194324 kb
Host smart-91cea2d1-8f6c-4f12-91d4-63825bbe8066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110282540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3110282540
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3542604375
Short name T259
Test name
Test status
Simulation time 38560937893 ps
CPU time 392.87 seconds
Started Jan 21 09:04:26 PM PST 24
Finished Jan 21 09:11:07 PM PST 24
Peak memory 197948 kb
Host smart-abd67e7a-699e-4b3c-91af-167b13b94085
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542604375 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3542604375
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.4164756277
Short name T217
Test name
Test status
Simulation time 584803443 ps
CPU time 0.96 seconds
Started Jan 21 09:04:39 PM PST 24
Finished Jan 21 09:04:44 PM PST 24
Peak memory 182584 kb
Host smart-6022c70c-2f44-4977-b734-10ae131370f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164756277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.4164756277
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2144953448
Short name T282
Test name
Test status
Simulation time 8239934624 ps
CPU time 13.32 seconds
Started Jan 21 09:04:31 PM PST 24
Finished Jan 21 09:04:51 PM PST 24
Peak memory 183140 kb
Host smart-7e401c57-0d88-450a-991f-033eb24076a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144953448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2144953448
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2823607630
Short name T180
Test name
Test status
Simulation time 592971296 ps
CPU time 0.71 seconds
Started Jan 21 09:04:26 PM PST 24
Finished Jan 21 09:04:35 PM PST 24
Peak memory 182892 kb
Host smart-353260ad-1573-4262-9a10-bb694e8e5cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823607630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2823607630
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2695804537
Short name T99
Test name
Test status
Simulation time 106230025868 ps
CPU time 155.94 seconds
Started Jan 21 09:04:35 PM PST 24
Finished Jan 21 09:07:15 PM PST 24
Peak memory 183080 kb
Host smart-5ae1a948-8c1b-4a8b-ad32-cafaa64e7caf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695804537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2695804537
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1398836370
Short name T92
Test name
Test status
Simulation time 420999505 ps
CPU time 0.69 seconds
Started Jan 21 09:04:34 PM PST 24
Finished Jan 21 09:04:39 PM PST 24
Peak memory 182960 kb
Host smart-4518660e-5c44-47df-b40e-90f4e0b032c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398836370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1398836370
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1810381746
Short name T160
Test name
Test status
Simulation time 56050815282 ps
CPU time 19.02 seconds
Started Jan 21 09:04:38 PM PST 24
Finished Jan 21 09:05:01 PM PST 24
Peak memory 183124 kb
Host smart-499efbbc-ed7e-41ed-8f4e-e34a18654c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810381746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1810381746
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1552320519
Short name T225
Test name
Test status
Simulation time 607087480 ps
CPU time 0.77 seconds
Started Jan 21 09:04:32 PM PST 24
Finished Jan 21 09:04:39 PM PST 24
Peak memory 183048 kb
Host smart-dda4c2ed-e6ef-4859-8625-23e0dc7d6038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552320519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1552320519
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1047562503
Short name T25
Test name
Test status
Simulation time 94992434339 ps
CPU time 33.02 seconds
Started Jan 21 09:04:36 PM PST 24
Finished Jan 21 09:05:14 PM PST 24
Peak memory 183352 kb
Host smart-508a1915-e5f1-4710-8c3f-1ec3626a0c97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047562503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1047562503
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3743488621
Short name T273
Test name
Test status
Simulation time 76849851509 ps
CPU time 598.49 seconds
Started Jan 21 09:04:29 PM PST 24
Finished Jan 21 09:14:35 PM PST 24
Peak memory 198004 kb
Host smart-aef3934d-b193-4d44-a77c-3d415dea57dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743488621 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3743488621
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3154592557
Short name T36
Test name
Test status
Simulation time 527813553 ps
CPU time 1.41 seconds
Started Jan 21 09:04:31 PM PST 24
Finished Jan 21 09:04:39 PM PST 24
Peak memory 183012 kb
Host smart-b1558cf2-f146-47b6-9741-1b92f281da14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154592557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3154592557
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2735985003
Short name T251
Test name
Test status
Simulation time 18826048001 ps
CPU time 32.77 seconds
Started Jan 21 09:04:32 PM PST 24
Finished Jan 21 09:05:11 PM PST 24
Peak memory 183136 kb
Host smart-15bb54f6-e50b-4068-93d1-5313a760c1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735985003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2735985003
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.367366149
Short name T119
Test name
Test status
Simulation time 441063026 ps
CPU time 0.61 seconds
Started Jan 21 09:04:37 PM PST 24
Finished Jan 21 09:04:42 PM PST 24
Peak memory 182888 kb
Host smart-647979aa-94ae-46ad-8d0a-9ca301087577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367366149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.367366149
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.323361695
Short name T235
Test name
Test status
Simulation time 390160856841 ps
CPU time 124.79 seconds
Started Jan 21 09:04:39 PM PST 24
Finished Jan 21 09:06:48 PM PST 24
Peak memory 182756 kb
Host smart-cc9388d9-784e-429c-9587-60658d4a8925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323361695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.323361695
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.79182596
Short name T191
Test name
Test status
Simulation time 340482511486 ps
CPU time 666.6 seconds
Started Jan 21 09:04:32 PM PST 24
Finished Jan 21 09:15:44 PM PST 24
Peak memory 199004 kb
Host smart-3a81d9c6-3e3f-456d-8b4c-92b573aaf221
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79182596 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.79182596
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.929540997
Short name T28
Test name
Test status
Simulation time 376163699 ps
CPU time 0.65 seconds
Started Jan 21 09:04:34 PM PST 24
Finished Jan 21 09:04:39 PM PST 24
Peak memory 183068 kb
Host smart-2be6657e-fd05-43de-b9c1-ca9b936921da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929540997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.929540997
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3822874324
Short name T197
Test name
Test status
Simulation time 38479344165 ps
CPU time 27.65 seconds
Started Jan 21 09:04:37 PM PST 24
Finished Jan 21 09:05:09 PM PST 24
Peak memory 183124 kb
Host smart-6669dd40-516b-46f9-b287-83bd4f0285d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822874324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3822874324
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3808458136
Short name T300
Test name
Test status
Simulation time 399686953 ps
CPU time 0.88 seconds
Started Jan 21 09:04:35 PM PST 24
Finished Jan 21 09:04:40 PM PST 24
Peak memory 182836 kb
Host smart-1823dfb6-ca7e-4df4-bf76-a3cd1aef38c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808458136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3808458136
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.435039561
Short name T83
Test name
Test status
Simulation time 201399800487 ps
CPU time 300.22 seconds
Started Jan 21 09:04:37 PM PST 24
Finished Jan 21 09:09:41 PM PST 24
Peak memory 194424 kb
Host smart-2c1525a5-33f1-4a69-8fd4-23e31aa67c90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435039561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.435039561
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1201703509
Short name T175
Test name
Test status
Simulation time 58692138797 ps
CPU time 114.7 seconds
Started Jan 21 09:04:37 PM PST 24
Finished Jan 21 09:06:36 PM PST 24
Peak memory 197960 kb
Host smart-d13d20f6-487e-4290-bcd2-a37ff64f0650
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201703509 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1201703509
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2552822584
Short name T23
Test name
Test status
Simulation time 357499902 ps
CPU time 1.17 seconds
Started Jan 21 09:02:06 PM PST 24
Finished Jan 21 09:02:23 PM PST 24
Peak memory 183060 kb
Host smart-ceca64e2-6e81-4759-8085-10bccab73106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552822584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2552822584
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.567483176
Short name T285
Test name
Test status
Simulation time 2961681430 ps
CPU time 4.81 seconds
Started Jan 21 09:02:01 PM PST 24
Finished Jan 21 09:02:22 PM PST 24
Peak memory 183016 kb
Host smart-79f09e27-ba05-424d-a325-101f8e6a0b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567483176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.567483176
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.289645855
Short name T240
Test name
Test status
Simulation time 491210890 ps
CPU time 0.95 seconds
Started Jan 21 09:02:06 PM PST 24
Finished Jan 21 09:02:23 PM PST 24
Peak memory 183060 kb
Host smart-a5e0b3aa-9a32-45f6-a8b4-baefdaef4196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289645855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.289645855
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2666032646
Short name T183
Test name
Test status
Simulation time 287968853835 ps
CPU time 177.04 seconds
Started Jan 21 09:02:06 PM PST 24
Finished Jan 21 09:05:20 PM PST 24
Peak memory 194520 kb
Host smart-c1c85807-3404-4545-9364-78aa703e2a39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666032646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2666032646
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1623639363
Short name T101
Test name
Test status
Simulation time 41596920685 ps
CPU time 181.05 seconds
Started Jan 21 10:05:55 PM PST 24
Finished Jan 21 10:09:03 PM PST 24
Peak memory 198004 kb
Host smart-248cba6a-fc1d-4412-bb8a-6debf235fdf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623639363 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1623639363
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3480278026
Short name T298
Test name
Test status
Simulation time 581251726 ps
CPU time 1.32 seconds
Started Jan 21 10:52:50 PM PST 24
Finished Jan 21 10:52:52 PM PST 24
Peak memory 183084 kb
Host smart-f5247e0e-9ca2-4b7a-a5c2-c575852a7aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480278026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3480278026
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3589311255
Short name T214
Test name
Test status
Simulation time 15929568143 ps
CPU time 23.64 seconds
Started Jan 21 09:01:59 PM PST 24
Finished Jan 21 09:02:39 PM PST 24
Peak memory 183088 kb
Host smart-7d1b4ad1-a214-42eb-909a-0e8d5ffa3dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589311255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3589311255
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.777557059
Short name T130
Test name
Test status
Simulation time 344795392 ps
CPU time 0.8 seconds
Started Jan 21 09:02:06 PM PST 24
Finished Jan 21 09:02:24 PM PST 24
Peak memory 183020 kb
Host smart-603312d6-80b0-474e-8699-d981fab240d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777557059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.777557059
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.4002994578
Short name T174
Test name
Test status
Simulation time 70786101386 ps
CPU time 26.79 seconds
Started Jan 21 09:15:04 PM PST 24
Finished Jan 21 09:15:33 PM PST 24
Peak memory 193456 kb
Host smart-0bc304f4-7755-48bd-bbda-47a18a3797a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002994578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.4002994578
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3682094169
Short name T177
Test name
Test status
Simulation time 88431851073 ps
CPU time 392.98 seconds
Started Jan 21 09:02:06 PM PST 24
Finished Jan 21 09:08:56 PM PST 24
Peak memory 197980 kb
Host smart-67e6c055-e1e8-4359-a101-0969059be87f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682094169 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3682094169
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2813345194
Short name T257
Test name
Test status
Simulation time 350043927 ps
CPU time 0.76 seconds
Started Jan 21 09:02:14 PM PST 24
Finished Jan 21 09:02:30 PM PST 24
Peak memory 182992 kb
Host smart-8ba7a652-12c1-430b-940b-ba37c81c3a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813345194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2813345194
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2560343220
Short name T137
Test name
Test status
Simulation time 28556406672 ps
CPU time 4.8 seconds
Started Jan 21 09:02:13 PM PST 24
Finished Jan 21 09:02:34 PM PST 24
Peak memory 183136 kb
Host smart-86b1dca2-16b8-4537-a116-066a16264a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560343220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2560343220
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.442203122
Short name T166
Test name
Test status
Simulation time 598779356 ps
CPU time 0.74 seconds
Started Jan 21 09:02:11 PM PST 24
Finished Jan 21 09:02:28 PM PST 24
Peak memory 182932 kb
Host smart-5bb7504c-ee0d-418d-a17e-dd139e4c7549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442203122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.442203122
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2236206463
Short name T283
Test name
Test status
Simulation time 138377191711 ps
CPU time 50.12 seconds
Started Jan 21 09:02:14 PM PST 24
Finished Jan 21 09:03:19 PM PST 24
Peak memory 183188 kb
Host smart-38f8d79d-31ad-446e-928a-05d727487bd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236206463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2236206463
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.624100842
Short name T140
Test name
Test status
Simulation time 221806948390 ps
CPU time 599.39 seconds
Started Jan 21 09:02:13 PM PST 24
Finished Jan 21 09:12:28 PM PST 24
Peak memory 199264 kb
Host smart-2b418376-d7ec-4839-8ab9-89399ef079f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624100842 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.624100842
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3236362198
Short name T163
Test name
Test status
Simulation time 363902578 ps
CPU time 0.72 seconds
Started Jan 21 09:02:10 PM PST 24
Finished Jan 21 09:02:27 PM PST 24
Peak memory 183056 kb
Host smart-641bea28-c200-495a-9907-17e7a98198a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236362198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3236362198
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.838759881
Short name T301
Test name
Test status
Simulation time 54734445505 ps
CPU time 20.47 seconds
Started Jan 21 09:02:15 PM PST 24
Finished Jan 21 09:02:50 PM PST 24
Peak memory 183060 kb
Host smart-61ff2649-0cea-42b9-9ed5-769fc68d736a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838759881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.838759881
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1817531248
Short name T195
Test name
Test status
Simulation time 570598956 ps
CPU time 1.38 seconds
Started Jan 21 09:02:12 PM PST 24
Finished Jan 21 09:02:29 PM PST 24
Peak memory 183000 kb
Host smart-2e4a2652-1cbf-4b25-aef3-e75f2ee23f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817531248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1817531248
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1643544538
Short name T112
Test name
Test status
Simulation time 127250455596 ps
CPU time 43.7 seconds
Started Jan 21 09:02:12 PM PST 24
Finished Jan 21 09:03:11 PM PST 24
Peak memory 194552 kb
Host smart-5d340476-6685-4408-a0b6-1fcf6f61101d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643544538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1643544538
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2777540347
Short name T181
Test name
Test status
Simulation time 233129933304 ps
CPU time 462.03 seconds
Started Jan 21 09:02:11 PM PST 24
Finished Jan 21 09:10:09 PM PST 24
Peak memory 197892 kb
Host smart-2ae18ee0-f095-4a9f-aac9-49a0dd3e763f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777540347 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2777540347
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2841655846
Short name T293
Test name
Test status
Simulation time 391719043 ps
CPU time 0.66 seconds
Started Jan 21 09:02:15 PM PST 24
Finished Jan 21 09:02:31 PM PST 24
Peak memory 183024 kb
Host smart-2a95926e-ebbe-4cd1-a27b-dfa5438991e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841655846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2841655846
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1661388552
Short name T148
Test name
Test status
Simulation time 7000396215 ps
CPU time 2.38 seconds
Started Jan 21 09:02:13 PM PST 24
Finished Jan 21 09:02:31 PM PST 24
Peak memory 183188 kb
Host smart-57aa8376-45a7-445b-a3ea-ec24488552e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661388552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1661388552
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.189539218
Short name T42
Test name
Test status
Simulation time 475135419 ps
CPU time 0.72 seconds
Started Jan 21 09:02:14 PM PST 24
Finished Jan 21 09:02:30 PM PST 24
Peak memory 182868 kb
Host smart-c78407fb-db4c-424a-a887-005e4fbe33b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189539218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.189539218
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.893717563
Short name T98
Test name
Test status
Simulation time 164790697783 ps
CPU time 61.59 seconds
Started Jan 21 09:02:18 PM PST 24
Finished Jan 21 09:03:34 PM PST 24
Peak memory 183132 kb
Host smart-b443ba3c-3bcb-4963-9895-f01d46369783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893717563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.893717563
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1837219978
Short name T253
Test name
Test status
Simulation time 604646369884 ps
CPU time 652.15 seconds
Started Jan 21 09:02:13 PM PST 24
Finished Jan 21 09:13:21 PM PST 24
Peak memory 199784 kb
Host smart-7e1848b0-976e-42dc-b402-444692e08deb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837219978 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1837219978
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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