Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	440983	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5895781	1		T1	231		T8	295		T2	114

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1572851	1		T1	172		T8	84		T2	45
values[0x0]	2244865	1		T1	131		T8	100		T2	37
values[0x1]	2519048	1		T1	116		T8	123		T2	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	198442	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	6138322	1		T1	281		T8	301		T2	114

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25389	1		T1	1		T13	1		T4	5
valid_sources[0x01]	25433	1		T8	1		T3	3		T11	3
valid_sources[0x02]	26430	1		T8	2		T3	1		T4	11
valid_sources[0x03]	23833	1		T1	2		T51	2		T55	3
valid_sources[0x04]	24490	1		T1	1		T8	2		T3	3
valid_sources[0x05]	25577	1		T24	1		T51	3		T82	1
valid_sources[0x06]	25340	1		T8	2		T3	1		T5	1
valid_sources[0x07]	25252	1		T1	1		T8	2		T13	2
valid_sources[0x08]	24857	1		T8	3		T13	1		T3	3
valid_sources[0x09]	25176	1		T4	2		T9	2		T11	19
valid_sources[0x0a]	24181	1		T2	19		T3	1		T5	1
valid_sources[0x0b]	24151	1		T8	1		T5	1		T51	2
valid_sources[0x0c]	23387	1		T8	2		T13	1		T3	12
valid_sources[0x0d]	26117	1		T1	2		T13	1		T3	10
valid_sources[0x0e]	24241	1		T1	3		T3	7		T6	4
valid_sources[0x0f]	26323	1		T1	1		T13	1		T3	2
valid_sources[0x10]	23914	1		T8	5		T5	2		T6	2
valid_sources[0x11]	25496	1		T8	1		T12	12		T3	5
valid_sources[0x12]	24593	1		T8	2		T4	10		T51	2
valid_sources[0x13]	21653	1		T1	1		T8	1		T3	1
valid_sources[0x14]	23921	1		T13	1		T3	12		T4	45
valid_sources[0x15]	25394	1		T1	1		T8	1		T13	2
valid_sources[0x16]	25837	1		T1	1		T13	1		T51	1
valid_sources[0x17]	24941	1		T1	4		T8	7		T13	1
valid_sources[0x18]	24124	1		T3	2		T51	1		T56	5
valid_sources[0x19]	24608	1		T10	1		T51	2		T56	1
valid_sources[0x1a]	25517	1		T1	1		T8	6		T51	5
valid_sources[0x1b]	25228	1		T1	3		T8	3		T51	1
valid_sources[0x1c]	27083	1		T51	4		T56	4		T52	2
valid_sources[0x1d]	25530	1		T8	2		T2	6		T3	1
valid_sources[0x1e]	23687	1		T8	1		T51	2		T82	1
valid_sources[0x1f]	23103	1		T1	4		T3	9		T51	2
valid_sources[0x20]	22799	1		T13	2		T3	1		T5	1
valid_sources[0x21]	23762	1		T1	3		T8	2		T3	7
valid_sources[0x22]	26761	1		T1	3		T8	1		T3	3
valid_sources[0x23]	24377	1		T8	1		T13	1		T6	2
valid_sources[0x24]	24505	1		T1	1		T8	1		T3	2
valid_sources[0x25]	26131	1		T1	2		T8	1		T9	2
valid_sources[0x26]	25182	1		T13	1		T51	3		T82	1
valid_sources[0x27]	24008	1		T1	2		T3	3		T5	1
valid_sources[0x28]	24525	1		T1	1		T8	1		T6	2
valid_sources[0x29]	23560	1		T8	1		T51	2		T56	3
valid_sources[0x2a]	23776	1		T8	2		T13	1		T3	2
valid_sources[0x2b]	27328	1		T1	3		T13	2		T3	1
valid_sources[0x2c]	23619	1		T8	2		T10	1		T51	1
valid_sources[0x2d]	23669	1		T1	3		T8	4		T5	1
valid_sources[0x2e]	24926	1		T8	4		T13	1		T51	2
valid_sources[0x2f]	25145	1		T1	1		T5	1		T51	1
valid_sources[0x30]	25025	1		T1	4		T8	2		T3	10
valid_sources[0x31]	24555	1		T1	1		T13	3		T51	7
valid_sources[0x32]	24056	1		T1	5		T13	2		T3	3
valid_sources[0x33]	25255	1		T1	4		T8	2		T3	1
valid_sources[0x34]	24777	1		T8	3		T10	3		T11	9
valid_sources[0x35]	25270	1		T8	2		T3	1		T6	1
valid_sources[0x36]	23615	1		T13	1		T128	2		T51	2
valid_sources[0x37]	22659	1		T11	4		T56	1		T52	2
valid_sources[0x38]	25078	1		T1	2		T3	3		T9	12
valid_sources[0x39]	26603	1		T8	2		T13	1		T5	1
valid_sources[0x3a]	23209	1		T13	1		T3	2		T4	14
valid_sources[0x3b]	23854	1		T1	1		T8	2		T13	1
valid_sources[0x3c]	27428	1		T1	1		T8	1		T3	3
valid_sources[0x3d]	25017	1		T8	5		T13	1		T3	5
valid_sources[0x3e]	24633	1		T13	1		T3	2		T51	5
valid_sources[0x3f]	25857	1		T1	3		T51	3		T56	6
valid_sources[0x40]	27228	1		T1	6		T3	1		T51	7
valid_sources[0x41]	24422	1		T1	2		T8	3		T13	1
valid_sources[0x42]	24460	1		T1	7		T8	2		T3	2
valid_sources[0x43]	25860	1		T1	1		T8	1		T51	2
valid_sources[0x44]	26242	1		T8	4		T5	1		T51	5
valid_sources[0x45]	24199	1		T1	1		T8	2		T13	1
valid_sources[0x46]	23930	1		T1	9		T9	3		T51	3
valid_sources[0x47]	24325	1		T1	5		T51	4		T56	7
valid_sources[0x48]	25015	1		T1	1		T8	2		T13	1
valid_sources[0x49]	25631	1		T3	4		T56	2		T52	2
valid_sources[0x4a]	26360	1		T5	1		T6	1		T9	4
valid_sources[0x4b]	25264	1		T1	1		T8	1		T55	1
valid_sources[0x4c]	26066	1		T13	1		T4	6		T5	6
valid_sources[0x4d]	24578	1		T1	2		T8	1		T3	1
valid_sources[0x4e]	24168	1		T1	1		T3	1		T5	1
valid_sources[0x4f]	24797	1		T51	1		T56	1		T52	2
valid_sources[0x50]	25870	1		T1	7		T8	5		T51	3
valid_sources[0x51]	24873	1		T1	4		T9	1		T56	5
valid_sources[0x52]	24587	1		T1	2		T8	2		T9	16
valid_sources[0x53]	23569	1		T51	1		T56	3		T52	2
valid_sources[0x54]	25477	1		T8	2		T3	4		T51	2
valid_sources[0x55]	26671	1		T8	2		T3	2		T10	10
valid_sources[0x56]	25581	1		T1	10		T8	1		T2	4
valid_sources[0x57]	26057	1		T1	6		T8	5		T13	1
valid_sources[0x58]	23889	1		T8	1		T13	1		T6	1
valid_sources[0x59]	24905	1		T1	1		T3	2		T9	9
valid_sources[0x5a]	25850	1		T4	22		T6	2		T51	2
valid_sources[0x5b]	24609	1		T1	7		T8	1		T3	4
valid_sources[0x5c]	24670	1		T1	4		T8	1		T10	6
valid_sources[0x5d]	24375	1		T3	3		T4	10		T9	13
valid_sources[0x5e]	23887	1		T8	1		T5	1		T6	1
valid_sources[0x5f]	22752	1		T1	1		T8	1		T51	1
valid_sources[0x60]	23450	1		T10	27		T51	3		T56	5
valid_sources[0x61]	22419	1		T1	1		T3	2		T5	2
valid_sources[0x62]	25978	1		T13	2		T11	6		T51	2
valid_sources[0x63]	24093	1		T1	1		T8	4		T13	1
valid_sources[0x64]	23944	1		T1	1		T3	1		T4	22
valid_sources[0x65]	26037	1		T8	2		T9	11		T51	3
valid_sources[0x66]	25932	1		T1	1		T13	1		T10	24
valid_sources[0x67]	24552	1		T10	5		T51	3		T56	5
valid_sources[0x68]	24629	1		T1	3		T8	2		T3	1
valid_sources[0x69]	25613	1		T13	1		T51	6		T56	3
valid_sources[0x6a]	25700	1		T1	2		T8	2		T2	14
valid_sources[0x6b]	24175	1		T1	3		T10	8		T51	2
valid_sources[0x6c]	25530	1		T8	2		T13	1		T3	6
valid_sources[0x6d]	25001	1		T8	1		T3	4		T51	3
valid_sources[0x6e]	24110	1		T1	3		T8	3		T3	2
valid_sources[0x6f]	24826	1		T8	1		T3	10		T21	5
valid_sources[0x70]	25144	1		T1	1		T8	6		T9	12
valid_sources[0x71]	25098	1		T51	2		T56	4		T52	1
valid_sources[0x72]	24194	1		T1	7		T51	3		T56	11
valid_sources[0x73]	25259	1		T1	4		T8	2		T56	5
valid_sources[0x74]	25110	1		T1	7		T8	1		T3	3
valid_sources[0x75]	24817	1		T8	2		T51	3		T56	3
valid_sources[0x76]	25129	1		T8	1		T9	3		T11	9
valid_sources[0x77]	25947	1		T8	1		T13	1		T10	11
valid_sources[0x78]	24167	1		T8	1		T13	1		T4	1
valid_sources[0x79]	25240	1		T1	2		T8	2		T5	1
valid_sources[0x7a]	23715	1		T1	1		T8	1		T13	1
valid_sources[0x7b]	25153	1		T3	4		T51	2		T55	1
valid_sources[0x7c]	23176	1		T1	1		T3	3		T4	11
valid_sources[0x7d]	23151	1		T1	1		T13	1		T3	2
valid_sources[0x7e]	25022	1		T1	10		T11	5		T51	3
valid_sources[0x7f]	24164	1		T1	2		T8	2		T3	20
valid_sources[0x80]	23690	1		T1	2		T3	2		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1475884

1

T1

68

T8

82

T2

44

values[0x0]

all_enables

biggest_size

2209784

1

T1

98

T8

100

T2

36

values[0x1]

all_enables

biggest_size

2210113

1

T1

65

T8

113

T2

34