Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	389885	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5249565	1		T1	12		T7	427		T2	109

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1400306	1		T1	11		T7	113		T8	1
values[0x0]	1999503	1		T1	5		T7	166		T2	62
values[0x1]	2239641	1		T1	7		T7	181		T2	58

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	176693	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5462757	1		T1	16		T7	449		T8	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21415	1		T1	1		T7	2		T2	2
valid_sources[0x01]	23597	1		T7	3		T2	1		T3	1
valid_sources[0x02]	23247	1		T7	1		T9	1		T10	4
valid_sources[0x03]	22229	1		T7	3		T15	9		T5	2
valid_sources[0x04]	22809	1		T2	3		T3	1		T4	1
valid_sources[0x05]	20992	1		T2	1		T3	2		T9	1
valid_sources[0x06]	20582	1		T7	5		T13	2		T3	3
valid_sources[0x07]	21608	1		T7	2		T2	1		T3	2
valid_sources[0x08]	21528	1		T7	2		T4	2		T9	2
valid_sources[0x09]	22839	1		T2	1		T4	1		T9	4
valid_sources[0x0a]	21281	1		T7	1		T2	1		T15	3
valid_sources[0x0b]	23478	1		T7	2		T2	1		T9	3
valid_sources[0x0c]	22587	1		T7	2		T4	2		T9	2
valid_sources[0x0d]	22541	1		T7	1		T3	1		T4	1
valid_sources[0x0e]	19626	1		T7	4		T2	1		T3	2
valid_sources[0x0f]	22443	1		T7	1		T2	1		T4	1
valid_sources[0x10]	23007	1		T7	2		T13	1		T9	2
valid_sources[0x11]	21217	1		T7	2		T2	2		T4	1
valid_sources[0x12]	23093	1		T7	3		T2	2		T3	1
valid_sources[0x13]	24138	1		T7	4		T2	2		T4	2
valid_sources[0x14]	21313	1		T7	1		T2	2		T3	2
valid_sources[0x15]	22666	1		T15	24		T3	1		T4	1
valid_sources[0x16]	22512	1		T7	2		T2	1		T9	1
valid_sources[0x17]	23858	1		T7	3		T3	1		T4	1
valid_sources[0x18]	22948	1		T7	1		T9	2		T5	1
valid_sources[0x19]	22617	1		T7	1		T2	1		T3	1
valid_sources[0x1a]	22225	1		T7	1		T4	2		T9	4
valid_sources[0x1b]	21600	1		T2	1		T14	20		T4	3
valid_sources[0x1c]	20209	1		T7	2		T2	1		T4	2
valid_sources[0x1d]	22780	1		T7	1		T10	2		T6	1
valid_sources[0x1e]	21785	1		T4	2		T5	1		T58	2
valid_sources[0x1f]	21555	1		T3	1		T4	1		T5	4
valid_sources[0x20]	21465	1		T1	1		T7	4		T9	5
valid_sources[0x21]	20803	1		T7	2		T2	1		T3	2
valid_sources[0x22]	23899	1		T7	2		T13	1		T3	1
valid_sources[0x23]	21957	1		T7	4		T2	2		T4	3
valid_sources[0x24]	22474	1		T7	2		T2	1		T9	2
valid_sources[0x25]	22292	1		T7	1		T2	1		T3	2
valid_sources[0x26]	21107	1		T7	2		T3	1		T4	1
valid_sources[0x27]	21005	1		T7	3		T3	1		T4	1
valid_sources[0x28]	23223	1		T7	2		T5	3		T10	2
valid_sources[0x29]	21443	1		T7	2		T2	1		T4	2
valid_sources[0x2a]	21849	1		T7	1		T2	2		T3	1
valid_sources[0x2b]	21096	1		T7	3		T4	1		T9	7
valid_sources[0x2c]	23030	1		T2	2		T3	1		T10	2
valid_sources[0x2d]	22131	1		T7	2		T3	1		T9	1
valid_sources[0x2e]	21945	1		T7	3		T2	1		T3	1
valid_sources[0x2f]	22774	1		T7	3		T2	1		T3	1
valid_sources[0x30]	21445	1		T7	1		T2	3		T3	2
valid_sources[0x31]	23360	1		T7	3		T2	1		T13	1
valid_sources[0x32]	24346	1		T7	4		T5	2		T10	1
valid_sources[0x33]	22121	1		T7	2		T15	10		T3	1
valid_sources[0x34]	21823	1		T7	3		T2	2		T4	3
valid_sources[0x35]	21626	1		T7	1		T9	1		T5	2
valid_sources[0x36]	22038	1		T7	2		T3	1		T4	3
valid_sources[0x37]	21725	1		T3	1		T4	2		T9	2
valid_sources[0x38]	20211	1		T7	1		T9	5		T5	2
valid_sources[0x39]	23281	1		T7	2		T2	1		T3	1
valid_sources[0x3a]	23129	1		T7	1		T3	3		T4	1
valid_sources[0x3b]	21482	1		T2	3		T3	1		T4	1
valid_sources[0x3c]	23343	1		T7	2		T2	1		T3	1
valid_sources[0x3d]	24139	1		T7	2		T2	1		T4	2
valid_sources[0x3e]	21998	1		T3	1		T9	2		T5	1
valid_sources[0x3f]	20249	1		T7	2		T2	1		T3	1
valid_sources[0x40]	22392	1		T7	3		T13	1		T3	1
valid_sources[0x41]	23617	1		T7	1		T2	2		T4	2
valid_sources[0x42]	22474	1		T7	1		T3	4		T9	2
valid_sources[0x43]	20806	1		T7	1		T2	3		T3	3
valid_sources[0x44]	21998	1		T7	2		T3	1		T9	1
valid_sources[0x45]	21518	1		T7	1		T2	2		T13	1
valid_sources[0x46]	20800	1		T2	1		T3	2		T9	1
valid_sources[0x47]	21562	1		T7	1		T3	1		T16	1
valid_sources[0x48]	20903	1		T7	2		T2	5		T3	1
valid_sources[0x49]	21557	1		T7	3		T2	2		T9	1
valid_sources[0x4a]	20399	1		T7	3		T2	1		T3	2
valid_sources[0x4b]	24059	1		T7	3		T16	1		T9	4
valid_sources[0x4c]	21411	1		T2	1		T3	1		T9	1
valid_sources[0x4d]	23534	1		T7	2		T3	1		T4	1
valid_sources[0x4e]	21403	1		T7	3		T2	1		T3	1
valid_sources[0x4f]	22555	1		T7	3		T2	2		T3	1
valid_sources[0x50]	22418	1		T1	1		T7	3		T2	1
valid_sources[0x51]	22941	1		T7	2		T2	1		T3	1
valid_sources[0x52]	22184	1		T7	2		T3	1		T4	2
valid_sources[0x53]	21980	1		T7	2		T2	1		T3	1
valid_sources[0x54]	22949	1		T7	4		T3	3		T9	2
valid_sources[0x55]	22104	1		T7	5		T3	1		T4	1
valid_sources[0x56]	22233	1		T7	1		T3	1		T12	4
valid_sources[0x57]	20998	1		T7	2		T3	1		T4	3
valid_sources[0x58]	21145	1		T7	3		T2	1		T3	1
valid_sources[0x59]	20833	1		T7	2		T9	2		T5	1
valid_sources[0x5a]	20466	1		T7	2		T3	1		T9	4
valid_sources[0x5b]	20976	1		T7	1		T3	1		T9	1
valid_sources[0x5c]	22622	1		T7	1		T2	1		T3	2
valid_sources[0x5d]	20798	1		T7	2		T2	2		T3	1
valid_sources[0x5e]	22366	1		T7	2		T2	3		T4	1
valid_sources[0x5f]	22599	1		T7	2		T2	3		T9	3
valid_sources[0x60]	20931	1		T3	1		T9	1		T10	1
valid_sources[0x61]	21573	1		T2	1		T3	1		T16	2
valid_sources[0x62]	22036	1		T7	1		T9	1		T5	1
valid_sources[0x63]	22600	1		T7	1		T3	2		T4	1
valid_sources[0x64]	22028	1		T7	1		T2	1		T9	1
valid_sources[0x65]	23090	1		T3	1		T9	4		T10	3
valid_sources[0x66]	22237	1		T2	1		T4	2		T9	1
valid_sources[0x67]	20456	1		T7	4		T3	1		T4	2
valid_sources[0x68]	22348	1		T7	2		T13	1		T15	19
valid_sources[0x69]	21604	1		T7	1		T2	1		T3	1
valid_sources[0x6a]	21688	1		T7	3		T2	2		T4	3
valid_sources[0x6b]	21722	1		T4	2		T9	1		T5	1
valid_sources[0x6c]	22019	1		T7	3		T3	1		T4	1
valid_sources[0x6d]	23136	1		T1	1		T7	2		T2	1
valid_sources[0x6e]	22699	1		T7	2		T5	1		T56	1
valid_sources[0x6f]	20129	1		T7	1		T9	2		T26	8
valid_sources[0x70]	22823	1		T1	1		T7	2		T9	2
valid_sources[0x71]	20922	1		T7	4		T2	1		T13	1
valid_sources[0x72]	21339	1		T7	1		T2	1		T3	1
valid_sources[0x73]	22270	1		T7	2		T2	1		T3	3
valid_sources[0x74]	22216	1		T1	1		T7	2		T2	1
valid_sources[0x75]	21981	1		T7	1		T2	1		T15	35
valid_sources[0x76]	22437	1		T7	2		T3	2		T56	3
valid_sources[0x77]	22480	1		T7	4		T3	1		T10	1
valid_sources[0x78]	21403	1		T7	2		T3	1		T9	2
valid_sources[0x79]	20456	1		T7	2		T9	2		T10	1
valid_sources[0x7a]	23491	1		T7	2		T2	2		T4	1
valid_sources[0x7b]	21242	1		T7	3		T2	2		T3	1
valid_sources[0x7c]	22762	1		T3	1		T9	1		T27	3
valid_sources[0x7d]	21568	1		T7	2		T3	1		T9	1
valid_sources[0x7e]	20651	1		T7	2		T13	1		T3	2
valid_sources[0x7f]	21601	1		T7	1		T4	2		T9	1
valid_sources[0x80]	21876	1		T7	2		T2	1		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1314334

1

T1

5

T7

107

T2

31

values[0x0]

all_enables

biggest_size

1968266

1

T1

4

T7

165

T2

41

values[0x1]

all_enables

biggest_size

1966965

1

T1

3

T7

155

T2

37