Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.30			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_ctrl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wkup_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_ctrl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_bark_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_bite_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wkup_count_cdc	98.21	100.00	92.86			100.00	100.00
tb.dut.u_reg.u_wdog_count_cdc	98.21	100.00	92.86			100.00	100.00
tb.dut.u_reg.u_wkup_cause_cdc	98.44	100.00	93.75			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_count_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.11	100.00	90.14			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_count_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.11	100.00	90.14			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.44	100.00	93.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	100.00	90.41			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 + DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wkup_ctrl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wkup_thold_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_bark_thold_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_bite_thold_cdc

SCORE	COND
98.21	92.86

tb.dut.u_reg.u_wkup_count_cdc

SCORE	COND
98.21	92.86

tb.dut.u_reg.u_wdog_count_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T3,T19,T20
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T18,T19,T20
1	1	Covered	T3,T19,T20

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.44	93.75

tb.dut.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T4
1	-	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T3,T18,T19
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T51,T52,T53
1	1	Covered	T3,T18,T19

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	34540551	0	0
DstReqKnown_A	29522944	28771656	0	0
SrcAckBusyChk_A	2147483647	38349	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34540551	0	0
T1	270648	15763	0	0
T2	3281840	111879	0	0
T3	1419760	152759	0	0
T4	385160	33586	0	0
T5	0	15463	0	0
T6	0	6225	0	0
T7	142376	0	0	0
T8	57784	0	0	0
T9	0	126565	0	0
T10	0	118030	0	0
T11	0	13070	0	0
T12	0	122499	0	0
T13	238784	0	0	0
T14	132008	0	0	0
T15	290504	0	0	0
T16	109360	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29522944	28771656	0	0
T1	536	48	0	0
T2	6824	256	0	0
T3	2832	2056	0	0
T4	3336	2072	0	0
T7	1176	536	0	0
T8	472	48	0	0
T13	480	8	0	0
T14	544	24	0	0
T15	568	40	0	0
T16	456	40	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38349	0	0
T1	270648	8	0	0
T2	3281840	67	0	0
T3	1419760	81	0	0
T4	385160	81	0	0
T5	0	80	0	0
T6	0	14	0	0
T7	142376	0	0	0
T8	57784	0	0	0
T9	0	143	0	0
T10	0	72	0	0
T11	0	16	0	0
T12	0	68	0	0
T13	238784	0	0	0
T14	132008	0	0	0
T15	290504	0	0	0
T16	109360	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	270648	270104	0	0
T2	3281840	3274960	0	0
T3	1419760	1418984	0	0
T4	385160	383592	0	0
T7	142376	141848	0	0
T8	57784	56992	0	0
T13	238784	238288	0	0
T14	132008	131408	0	0
T15	290504	289768	0	0
T16	109360	108720	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	775923878	5893396	0	0
DstReqKnown_A	3690368	3596457	0	0
SrcAckBusyChk_A	775923878	6721	0	0
SrcBusyKnown_A	775923878	775200321	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	5893396	0	0
T1	33831	1964	0	0
T2	410230	14795	0	0
T3	177470	9932	0	0
T4	48145	4827	0	0
T5	0	1899	0	0
T6	0	832	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	15636	0	0
T10	0	14830	0	0
T11	0	1637	0	0
T12	0	7747	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3690368	3596457	0	0
T1	67	6	0	0
T2	853	32	0	0
T3	354	257	0	0
T4	417	259	0	0
T7	147	67	0	0
T8	59	6	0	0
T13	60	1	0	0
T14	68	3	0	0
T15	71	5	0	0
T16	57	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	6721	0	0
T1	33831	1	0	0
T2	410230	9	0	0
T3	177470	6	0	0
T4	48145	12	0	0
T5	0	10	0	0
T6	0	2	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	18	0	0
T10	0	9	0	0
T11	0	2	0	0
T12	0	5	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	775200321	0	0
T1	33831	33763	0	0
T2	410230	409370	0	0
T3	177470	177373	0	0
T4	48145	47949	0	0
T7	17797	17731	0	0
T8	7223	7124	0	0
T13	29848	29786	0	0
T14	16501	16426	0	0
T15	36313	36221	0	0
T16	13670	13590	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	775923878	2938230	0	0
DstReqKnown_A	3690368	3596457	0	0
SrcAckBusyChk_A	775923878	3460	0	0
SrcBusyKnown_A	775923878	775200321	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	2938230	0	0
T1	33831	1976	0	0
T2	410230	14871	0	0
T3	177470	8459	0	0
T4	48145	2290	0	0
T5	0	1903	0	0
T6	0	826	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	13904	0	0
T10	0	14772	0	0
T11	0	1617	0	0
T12	0	18038	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3690368	3596457	0	0
T1	67	6	0	0
T2	853	32	0	0
T3	354	257	0	0
T4	417	259	0	0
T7	147	67	0	0
T8	59	6	0	0
T13	60	1	0	0
T14	68	3	0	0
T15	71	5	0	0
T16	57	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	3460	0	0
T1	33831	1	0	0
T2	410230	9	0	0
T3	177470	5	0	0
T4	48145	6	0	0
T5	0	10	0	0
T6	0	2	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	16	0	0
T10	0	9	0	0
T11	0	2	0	0
T12	0	11	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	775200321	0	0
T1	33831	33763	0	0
T2	410230	409370	0	0
T3	177470	177373	0	0
T4	48145	47949	0	0
T7	17797	17731	0	0
T8	7223	7124	0	0
T13	29848	29786	0	0
T14	16501	16426	0	0
T15	36313	36221	0	0
T16	13670	13590	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	775923878	5194901	0	0
DstReqKnown_A	3690368	3596457	0	0
SrcAckBusyChk_A	775923878	5874	0	0
SrcBusyKnown_A	775923878	775200321	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	5194901	0	0
T1	33831	1962	0	0
T2	410230	14765	0	0
T3	177470	32930	0	0
T4	48145	4632	0	0
T5	0	1913	0	0
T6	0	455	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	16640	0	0
T10	0	14693	0	0
T11	0	1643	0	0
T12	0	7792	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3690368	3596457	0	0
T1	67	6	0	0
T2	853	32	0	0
T3	354	257	0	0
T4	417	259	0	0
T7	147	67	0	0
T8	59	6	0	0
T13	60	1	0	0
T14	68	3	0	0
T15	71	5	0	0
T16	57	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	5874	0	0
T1	33831	1	0	0
T2	410230	9	0	0
T3	177470	19	0	0
T4	48145	12	0	0
T5	0	10	0	0
T6	0	1	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	19	0	0
T10	0	9	0	0
T11	0	2	0	0
T12	0	5	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	775200321	0	0
T1	33831	33763	0	0
T2	410230	409370	0	0
T3	177470	177373	0	0
T4	48145	47949	0	0
T7	17797	17731	0	0
T8	7223	7124	0	0
T13	29848	29786	0	0
T14	16501	16426	0	0
T15	36313	36221	0	0
T16	13670	13590	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	775923878	2942062	0	0
DstReqKnown_A	3690368	3596457	0	0
SrcAckBusyChk_A	775923878	3490	0	0
SrcBusyKnown_A	775923878	775200321	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	2942062	0	0
T1	33831	1974	0	0
T2	410230	12530	0	0
T3	177470	25433	0	0
T4	48145	5631	0	0
T5	0	1945	0	0
T6	0	779	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	15297	0	0
T10	0	14823	0	0
T11	0	1633	0	0
T12	0	4906	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3690368	3596457	0	0
T1	67	6	0	0
T2	853	32	0	0
T3	354	257	0	0
T4	417	259	0	0
T7	147	67	0	0
T8	59	6	0	0
T13	60	1	0	0
T14	68	3	0	0
T15	71	5	0	0
T16	57	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	3490	0	0
T1	33831	1	0	0
T2	410230	7	0	0
T3	177470	15	0	0
T4	48145	14	0	0
T5	0	10	0	0
T6	0	2	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	16	0	0
T10	0	9	0	0
T11	0	2	0	0
T12	0	3	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	775200321	0	0
T1	33831	33763	0	0
T2	410230	409370	0	0
T3	177470	177373	0	0
T4	48145	47949	0	0
T7	17797	17731	0	0
T8	7223	7124	0	0
T13	29848	29786	0	0
T14	16501	16426	0	0
T15	36313	36221	0	0
T16	13670	13590	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	775923878	2993138	0	0
DstReqKnown_A	3690368	3596457	0	0
SrcAckBusyChk_A	775923878	3534	0	0
SrcBusyKnown_A	775923878	775200321	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	2993138	0	0
T1	33831	1968	0	0
T2	410230	14697	0	0
T3	177470	15447	0	0
T4	48145	6199	0	0
T5	0	1936	0	0
T6	0	786	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	16676	0	0
T10	0	14681	0	0
T11	0	1635	0	0
T12	0	19586	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3690368	3596457	0	0
T1	67	6	0	0
T2	853	32	0	0
T3	354	257	0	0
T4	417	259	0	0
T7	147	67	0	0
T8	59	6	0	0
T13	60	1	0	0
T14	68	3	0	0
T15	71	5	0	0
T16	57	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	3534	0	0
T1	33831	1	0	0
T2	410230	9	0	0
T3	177470	9	0	0
T4	48145	16	0	0
T5	0	10	0	0
T6	0	2	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	19	0	0
T10	0	9	0	0
T11	0	2	0	0
T12	0	12	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	775200321	0	0
T1	33831	33763	0	0
T2	410230	409370	0	0
T3	177470	177373	0	0
T4	48145	47949	0	0
T7	17797	17731	0	0
T8	7223	7124	0	0
T13	29848	29786	0	0
T14	16501	16426	0	0
T15	36313	36221	0	0
T16	13670	13590	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T19,T20,T21
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T18,T19,T20
1	1	Covered	T19,T20,T21

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	775923878	6183659	0	0
DstReqKnown_A	3690368	3596457	0	0
SrcAckBusyChk_A	775923878	6232	0	0
SrcBusyKnown_A	775923878	775200321	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	6183659	0	0
T1	33831	1972	0	0
T2	410230	12935	0	0
T3	177470	31515	0	0
T4	48145	2951	0	0
T5	0	1962	0	0
T6	0	1037	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	16747	0	0
T10	0	14807	0	0
T11	0	1637	0	0
T12	0	22775	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3690368	3596457	0	0
T1	67	6	0	0
T2	853	32	0	0
T3	354	257	0	0
T4	417	259	0	0
T7	147	67	0	0
T8	59	6	0	0
T13	60	1	0	0
T14	68	3	0	0
T15	71	5	0	0
T16	57	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	6232	0	0
T1	33831	1	0	0
T2	410230	8	0	0
T3	177470	14	0	0
T4	48145	6	0	0
T5	0	10	0	0
T6	0	2	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	19	0	0
T10	0	9	0	0
T11	0	2	0	0
T12	0	11	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	775200321	0	0
T1	33831	33763	0	0
T2	410230	409370	0	0
T3	177470	177373	0	0
T4	48145	47949	0	0
T7	17797	17731	0	0
T8	7223	7124	0	0
T13	29848	29786	0	0
T14	16501	16426	0	0
T15	36313	36221	0	0
T16	13670	13590	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T3,T19,T20
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T18,T19,T24
1	1	Covered	T3,T19,T20

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	775923878	5762424	0	0
DstReqKnown_A	3690368	3596457	0	0
SrcAckBusyChk_A	775923878	6209	0	0
SrcBusyKnown_A	775923878	775200321	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	5762424	0	0
T1	33831	1981	0	0
T2	410230	12539	0	0
T3	177470	5589	0	0
T4	48145	2393	0	0
T5	0	1952	0	0
T6	0	1059	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	16663	0	0
T10	0	14701	0	0
T11	0	1625	0	0
T12	0	10560	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3690368	3596457	0	0
T1	67	6	0	0
T2	853	32	0	0
T3	354	257	0	0
T4	417	259	0	0
T7	147	67	0	0
T8	59	6	0	0
T13	60	1	0	0
T14	68	3	0	0
T15	71	5	0	0
T16	57	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	6209	0	0
T1	33831	1	0	0
T2	410230	7	0	0
T3	177470	2	0	0
T4	48145	5	0	0
T5	0	10	0	0
T6	0	2	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	19	0	0
T10	0	9	0	0
T11	0	2	0	0
T12	0	6	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	775200321	0	0
T1	33831	33763	0	0
T2	410230	409370	0	0
T3	177470	177373	0	0
T4	48145	47949	0	0
T7	17797	17731	0	0
T8	7223	7124	0	0
T13	29848	29786	0	0
T14	16501	16426	0	0
T15	36313	36221	0	0
T16	13670	13590	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T4
1	-	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T3,T18,T19
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T51,T52,T53
1	1	Covered	T3,T18,T19

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T7,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	775923878	2632741	0	0
DstReqKnown_A	3690368	3596457	0	0
SrcAckBusyChk_A	775923878	2829	0	0
SrcBusyKnown_A	775923878	775200321	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	2632741	0	0
T1	33831	1966	0	0
T2	410230	14747	0	0
T3	177470	23454	0	0
T4	48145	4663	0	0
T5	0	1953	0	0
T6	0	451	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	15002	0	0
T10	0	14723	0	0
T11	0	1643	0	0
T12	0	31095	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3690368	3596457	0	0
T1	67	6	0	0
T2	853	32	0	0
T3	354	257	0	0
T4	417	259	0	0
T7	147	67	0	0
T8	59	6	0	0
T13	60	1	0	0
T14	68	3	0	0
T15	71	5	0	0
T16	57	5	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	2829	0	0
T1	33831	1	0	0
T2	410230	9	0	0
T3	177470	11	0	0
T4	48145	10	0	0
T5	0	10	0	0
T6	0	1	0	0
T7	17797	0	0	0
T8	7223	0	0	0
T9	0	17	0	0
T10	0	9	0	0
T11	0	2	0	0
T12	0	15	0	0
T13	29848	0	0	0
T14	16501	0	0	0
T15	36313	0	0	0
T16	13670	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	775923878	775200321	0	0
T1	33831	33763	0	0
T2	410230	409370	0	0
T3	177470	177373	0	0
T4	48145	47949	0	0
T7	17797	17731	0	0
T8	7223	7124	0	0
T13	29848	29786	0	0
T14	16501	16426	0	0
T15	36313	36221	0	0
T16	13670	13590	0	0