Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	664574719	7107115	0	0
wdog_bark_thold_rd_A	664574719	42244	0	0
wdog_bite_thold_rd_A	664574719	37806	0	0
wdog_ctrl_rd_A	664574719	37251	0	0
wdog_regwen_rd_A	664574719	42680	0	0
wkup_ctrl_rd_A	664574719	37095	0	0
wkup_thold_rd_A	664574719	42139	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	7107115	0	0
T1	412703	4	0	0
T2	21978	0	0	0
T3	9263	0	0	0
T8	41643	0	0	0
T9	0	7	0	0
T10	0	3	0	0
T11	0	125	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	736	0	0
T22	0	62632	0	0
T23	0	66552	0	0
T25	0	98222	0	0
T28	0	630	0	0
T30	0	4	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	42244	0	0
T4	11341	0	0	0
T5	12269	0	0	0
T6	49226	0	0	0
T9	205807	0	0	0
T10	190352	0	0	0
T17	24738	48	0	0
T26	35769	0	0	0
T27	41398	0	0	0
T28	6710	0	0	0
T30	0	77	0	0
T49	0	8342	0	0
T51	0	6721	0	0
T55	0	107	0	0
T56	7428	0	0	0
T78	0	5931	0	0
T79	0	10725	0	0
T80	0	2526	0	0
T81	0	6806	0	0
T82	0	2	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	37806	0	0
T4	11341	0	0	0
T5	12269	0	0	0
T6	49226	0	0	0
T9	205807	0	0	0
T10	190352	0	0	0
T17	24738	15	0	0
T26	35769	0	0	0
T27	41398	0	0	0
T28	6710	0	0	0
T30	0	71	0	0
T49	0	7038	0	0
T51	0	5627	0	0
T55	0	144	0	0
T56	7428	0	0	0
T78	0	5730	0	0
T79	0	9754	0	0
T80	0	2086	0	0
T81	0	6293	0	0
T82	0	4	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	37251	0	0
T4	11341	0	0	0
T5	12269	0	0	0
T6	49226	0	0	0
T9	205807	0	0	0
T10	190352	0	0	0
T17	24738	43	0	0
T26	35769	0	0	0
T27	41398	0	0	0
T28	6710	0	0	0
T30	0	93	0	0
T49	0	7238	0	0
T51	0	5701	0	0
T55	0	128	0	0
T56	7428	0	0	0
T78	0	5413	0	0
T79	0	9759	0	0
T80	0	1967	0	0
T81	0	5851	0	0
T83	0	8	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	42680	0	0
T4	11341	0	0	0
T5	12269	0	0	0
T6	49226	0	0	0
T9	205807	0	0	0
T10	190352	0	0	0
T17	24738	54	0	0
T26	35769	0	0	0
T27	41398	0	0	0
T28	6710	0	0	0
T30	0	62	0	0
T49	0	7684	0	0
T51	0	6552	0	0
T55	0	249	0	0
T56	7428	0	0	0
T78	0	6142	0	0
T79	0	11101	0	0
T80	0	2354	0	0
T81	0	7130	0	0
T83	0	8	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	37095	0	0
T4	11341	0	0	0
T5	12269	0	0	0
T6	49226	0	0	0
T9	205807	0	0	0
T10	190352	0	0	0
T17	24738	19	0	0
T26	35769	2	0	0
T27	41398	0	0	0
T28	6710	0	0	0
T30	0	82	0	0
T49	0	6705	0	0
T51	0	5798	0	0
T55	0	125	0	0
T56	7428	0	0	0
T78	0	5281	0	0
T79	0	9555	0	0
T80	0	2094	0	0
T81	0	6245	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	42139	0	0
T4	11341	0	0	0
T5	12269	0	0	0
T6	49226	0	0	0
T9	205807	0	0	0
T10	190352	0	0	0
T17	24738	28	0	0
T26	35769	0	0	0
T27	41398	0	0	0
T28	6710	0	0	0
T30	0	77	0	0
T49	0	7682	0	0
T51	0	6487	0	0
T55	0	81	0	0
T56	7428	0	0	0
T78	0	6248	0	0
T79	0	11025	0	0
T80	0	2163	0	0
T81	0	7346	0	0
T83	0	5	0	0