Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.30			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_ctrl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wkup_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_ctrl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_bark_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wdog_bite_thold_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_wkup_count_cdc	98.21	100.00	92.86			100.00	100.00
tb.dut.u_reg.u_wdog_count_cdc	98.21	100.00	92.86			100.00	100.00
tb.dut.u_reg.u_wkup_cause_cdc	98.44	100.00	93.75			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_count_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.11	100.00	90.14			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wdog_count_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.11	100.00	90.14			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.44	100.00	93.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	100.00	90.41			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.51	100.00	98.05			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 + DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wkup_ctrl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wkup_thold_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_bark_thold_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_bite_thold_cdc

SCORE	COND
98.21	92.86

tb.dut.u_reg.u_wkup_count_cdc

SCORE	COND
98.21	92.86

tb.dut.u_reg.u_wdog_count_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T7,T18,T20
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T19,T21,T31
1	1	Covered	T7,T18,T20

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.44	93.75

tb.dut.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T9
1	-	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T7,T18,T19
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T22,T23,T25
1	1	Covered	T7,T18,T19

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	29117142	0	0
DstReqKnown_A	26938824	26165848	0	0
SrcAckBusyChk_A	2147483647	36692	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	29117142	0	0
T1	3301624	120549	0	0
T2	175824	15024	0	0
T3	74104	3768	0	0
T4	0	3863	0	0
T5	0	7231	0	0
T6	0	39735	0	0
T8	333144	0	0	0
T9	0	56407	0	0
T10	0	58412	0	0
T12	98608	0	0	0
T13	29496	0	0	0
T14	47136	0	0	0
T15	29560	0	0	0
T16	18936	0	0	0
T17	197904	0	0	0
T26	0	700	0	0
T54	0	196	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26938824	26165848	0	0
T1	13752	600	0	0
T2	712	88	0	0
T3	600	56	0	0
T8	656	16	0	0
T12	816	48	0	0
T13	976	176	0	0
T14	456	56	0	0
T15	832	96	0	0
T16	624	144	0	0
T17	1640	920	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36692	0	0
T1	3301624	152	0	0
T2	175824	15	0	0
T3	74104	8	0	0
T4	0	8	0	0
T5	0	16	0	0
T6	0	43	0	0
T7	0	16	0	0
T8	333144	0	0	0
T9	0	152	0	0
T10	0	144	0	0
T11	0	6	0	0
T12	98608	0	0	0
T13	29496	0	0	0
T14	47136	0	0	0
T15	29560	0	0	0
T16	18936	0	0	0
T17	197904	0	0	0
T55	0	252	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3301624	3289496	0	0
T2	175824	175128	0	0
T3	74104	73424	0	0
T8	333144	332448	0	0
T12	98608	98160	0	0
T13	29496	28936	0	0
T14	47136	46344	0	0
T15	29560	28800	0	0
T16	18936	18440	0	0
T17	197904	197456	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	664574719	4922394	0	0
DstReqKnown_A	3367353	3270731	0	0
SrcAckBusyChk_A	664574719	6395	0	0
SrcBusyKnown_A	664574719	663955259	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	4922394	0	0
T1	412703	15104	0	0
T2	21978	1957	0	0
T3	9263	467	0	0
T4	0	438	0	0
T5	0	875	0	0
T6	0	4017	0	0
T8	41643	0	0	0
T9	0	7049	0	0
T10	0	7337	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0
T26	0	141	0	0
T54	0	46	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3367353	3270731	0	0
T1	1719	75	0	0
T2	89	11	0	0
T3	75	7	0	0
T8	82	2	0	0
T12	102	6	0	0
T13	122	22	0	0
T14	57	7	0	0
T15	104	12	0	0
T16	78	18	0	0
T17	205	115	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	6395	0	0
T1	412703	19	0	0
T2	21978	2	0	0
T3	9263	1	0	0
T4	0	1	0	0
T5	0	2	0	0
T6	0	5	0	0
T7	0	2	0	0
T8	41643	0	0	0
T9	0	19	0	0
T10	0	18	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0
T55	0	48	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	663955259	0	0
T1	412703	411187	0	0
T2	21978	21891	0	0
T3	9263	9178	0	0
T8	41643	41556	0	0
T12	12326	12270	0	0
T13	3687	3617	0	0
T14	5892	5793	0	0
T15	3695	3600	0	0
T16	2367	2305	0	0
T17	24738	24682	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	664574719	2477212	0	0
DstReqKnown_A	3367353	3270731	0	0
SrcAckBusyChk_A	664574719	3269	0	0
SrcBusyKnown_A	664574719	663955259	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	2477212	0	0
T1	412703	15067	0	0
T2	21978	1943	0	0
T3	9263	479	0	0
T4	0	496	0	0
T5	0	880	0	0
T6	0	1561	0	0
T8	41643	0	0	0
T9	0	7344	0	0
T10	0	7191	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0
T26	0	99	0	0
T54	0	24	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3367353	3270731	0	0
T1	1719	75	0	0
T2	89	11	0	0
T3	75	7	0	0
T8	82	2	0	0
T12	102	6	0	0
T13	122	22	0	0
T14	57	7	0	0
T15	104	12	0	0
T16	78	18	0	0
T17	205	115	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	3269	0	0
T1	412703	19	0	0
T2	21978	2	0	0
T3	9263	1	0	0
T4	0	1	0	0
T5	0	2	0	0
T6	0	2	0	0
T7	0	2	0	0
T8	41643	0	0	0
T9	0	19	0	0
T10	0	18	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0
T55	0	50	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	663955259	0	0
T1	412703	411187	0	0
T2	21978	21891	0	0
T3	9263	9178	0	0
T8	41643	41556	0	0
T12	12326	12270	0	0
T13	3687	3617	0	0
T14	5892	5793	0	0
T15	3695	3600	0	0
T16	2367	2305	0	0
T17	24738	24682	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	664574719	4326403	0	0
DstReqKnown_A	3367353	3270731	0	0
SrcAckBusyChk_A	664574719	5550	0	0
SrcBusyKnown_A	664574719	663955259	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	4326403	0	0
T1	412703	15137	0	0
T2	21978	1932	0	0
T3	9263	463	0	0
T4	0	501	0	0
T5	0	950	0	0
T6	0	5590	0	0
T8	41643	0	0	0
T9	0	7153	0	0
T10	0	7133	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0
T26	0	54	0	0
T54	0	14	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3367353	3270731	0	0
T1	1719	75	0	0
T2	89	11	0	0
T3	75	7	0	0
T8	82	2	0	0
T12	102	6	0	0
T13	122	22	0	0
T14	57	7	0	0
T15	104	12	0	0
T16	78	18	0	0
T17	205	115	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	5550	0	0
T1	412703	19	0	0
T2	21978	2	0	0
T3	9263	1	0	0
T4	0	1	0	0
T5	0	2	0	0
T6	0	7	0	0
T7	0	2	0	0
T8	41643	0	0	0
T9	0	19	0	0
T10	0	18	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0
T55	0	53	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	663955259	0	0
T1	412703	411187	0	0
T2	21978	21891	0	0
T3	9263	9178	0	0
T8	41643	41556	0	0
T12	12326	12270	0	0
T13	3687	3617	0	0
T14	5892	5793	0	0
T15	3695	3600	0	0
T16	2367	2305	0	0
T17	24738	24682	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	664574719	2482434	0	0
DstReqKnown_A	3367353	3270731	0	0
SrcAckBusyChk_A	664574719	3264	0	0
SrcBusyKnown_A	664574719	663955259	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	2482434	0	0
T1	412703	15068	0	0
T2	21978	1934	0	0
T3	9263	473	0	0
T4	0	478	0	0
T5	0	894	0	0
T6	0	4917	0	0
T8	41643	0	0	0
T9	0	6880	0	0
T10	0	7228	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0
T26	0	22	0	0
T54	0	34	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3367353	3270731	0	0
T1	1719	75	0	0
T2	89	11	0	0
T3	75	7	0	0
T8	82	2	0	0
T12	102	6	0	0
T13	122	22	0	0
T14	57	7	0	0
T15	104	12	0	0
T16	78	18	0	0
T17	205	115	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	3264	0	0
T1	412703	19	0	0
T2	21978	2	0	0
T3	9263	1	0	0
T4	0	1	0	0
T5	0	2	0	0
T6	0	6	0	0
T7	0	2	0	0
T8	41643	0	0	0
T9	0	19	0	0
T10	0	18	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0
T55	0	49	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	663955259	0	0
T1	412703	411187	0	0
T2	21978	21891	0	0
T3	9263	9178	0	0
T8	41643	41556	0	0
T12	12326	12270	0	0
T13	3687	3617	0	0
T14	5892	5793	0	0
T15	3695	3600	0	0
T16	2367	2305	0	0
T17	24738	24682	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	664574719	2449430	0	0
DstReqKnown_A	3367353	3270731	0	0
SrcAckBusyChk_A	664574719	3247	0	0
SrcBusyKnown_A	664574719	663955259	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	2449430	0	0
T1	412703	14852	0	0
T2	21978	1935	0	0
T3	9263	471	0	0
T4	0	480	0	0
T5	0	907	0	0
T6	0	2449	0	0
T8	41643	0	0	0
T9	0	7043	0	0
T10	0	7435	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0
T26	0	97	0	0
T54	0	34	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3367353	3270731	0	0
T1	1719	75	0	0
T2	89	11	0	0
T3	75	7	0	0
T8	82	2	0	0
T12	102	6	0	0
T13	122	22	0	0
T14	57	7	0	0
T15	104	12	0	0
T16	78	18	0	0
T17	205	115	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	3247	0	0
T1	412703	19	0	0
T2	21978	2	0	0
T3	9263	1	0	0
T4	0	1	0	0
T5	0	2	0	0
T6	0	3	0	0
T7	0	2	0	0
T8	41643	0	0	0
T9	0	19	0	0
T10	0	18	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0
T55	0	52	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	663955259	0	0
T1	412703	411187	0	0
T2	21978	21891	0	0
T3	9263	9178	0	0
T8	41643	41556	0	0
T12	12326	12270	0	0
T13	3687	3617	0	0
T14	5892	5793	0	0
T15	3695	3600	0	0
T16	2367	2305	0	0
T17	24738	24682	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T18,T20,T22
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T19,T21,T31
1	1	Covered	T18,T20,T22

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	664574719	5276853	0	0
DstReqKnown_A	3367353	3270731	0	0
SrcAckBusyChk_A	664574719	6115	0	0
SrcBusyKnown_A	664574719	663955259	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	5276853	0	0
T1	412703	15096	0	0
T2	21978	2179	0	0
T3	9263	481	0	0
T4	0	496	0	0
T5	0	942	0	0
T6	0	12347	0	0
T8	41643	0	0	0
T9	0	6897	0	0
T10	0	7437	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0
T26	0	118	0	0
T54	0	6	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3367353	3270731	0	0
T1	1719	75	0	0
T2	89	11	0	0
T3	75	7	0	0
T8	82	2	0	0
T12	102	6	0	0
T13	122	22	0	0
T14	57	7	0	0
T15	104	12	0	0
T16	78	18	0	0
T17	205	115	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	6115	0	0
T1	412703	19	0	0
T2	21978	2	0	0
T3	9263	1	0	0
T4	0	1	0	0
T5	0	2	0	0
T6	0	12	0	0
T7	0	2	0	0
T8	41643	0	0	0
T9	0	19	0	0
T10	0	18	0	0
T11	0	2	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	663955259	0	0
T1	412703	411187	0	0
T2	21978	21891	0	0
T3	9263	9178	0	0
T8	41643	41556	0	0
T12	12326	12270	0	0
T13	3687	3617	0	0
T14	5892	5793	0	0
T15	3695	3600	0	0
T16	2367	2305	0	0
T17	24738	24682	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T7,T22,T23
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T31,T23,T25
1	1	Covered	T7,T22,T23

---

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	664574719	4940559	0	0
DstReqKnown_A	3367353	3270731	0	0
SrcAckBusyChk_A	664574719	6107	0	0
SrcBusyKnown_A	664574719	663955259	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	4940559	0	0
T1	412703	15046	0	0
T2	21978	954	0	0
T3	9263	469	0	0
T4	0	496	0	0
T5	0	876	0	0
T6	0	3691	0	0
T8	41643	0	0	0
T9	0	7073	0	0
T10	0	7321	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0
T26	0	91	0	0
T54	0	26	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3367353	3270731	0	0
T1	1719	75	0	0
T2	89	11	0	0
T3	75	7	0	0
T8	82	2	0	0
T12	102	6	0	0
T13	122	22	0	0
T14	57	7	0	0
T15	104	12	0	0
T16	78	18	0	0
T17	205	115	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	6107	0	0
T1	412703	19	0	0
T2	21978	1	0	0
T3	9263	1	0	0
T4	0	1	0	0
T5	0	2	0	0
T6	0	3	0	0
T7	0	2	0	0
T8	41643	0	0	0
T9	0	19	0	0
T10	0	18	0	0
T11	0	2	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	663955259	0	0
T1	412703	411187	0	0
T2	21978	21891	0	0
T3	9263	9178	0	0
T8	41643	41556	0	0
T12	12326	12270	0	0
T13	3687	3617	0	0
T14	5892	5793	0	0
T15	3695	3600	0	0
T16	2367	2305	0	0
T17	24738	24682	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T9
1	-	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T7,T18,T19
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T22,T23,T25
1	1	Covered	T7,T18,T19

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T8
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	664574719	2241857	0	0
DstReqKnown_A	3367353	3270731	0	0
SrcAckBusyChk_A	664574719	2745	0	0
SrcBusyKnown_A	664574719	663955259	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	2241857	0	0
T1	412703	15179	0	0
T2	21978	2190	0	0
T3	9263	465	0	0
T4	0	478	0	0
T5	0	907	0	0
T6	0	5163	0	0
T8	41643	0	0	0
T9	0	6968	0	0
T10	0	7330	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0
T26	0	78	0	0
T54	0	12	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3367353	3270731	0	0
T1	1719	75	0	0
T2	89	11	0	0
T3	75	7	0	0
T8	82	2	0	0
T12	102	6	0	0
T13	122	22	0	0
T14	57	7	0	0
T15	104	12	0	0
T16	78	18	0	0
T17	205	115	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	2745	0	0
T1	412703	19	0	0
T2	21978	2	0	0
T3	9263	1	0	0
T4	0	1	0	0
T5	0	2	0	0
T6	0	5	0	0
T7	0	2	0	0
T8	41643	0	0	0
T9	0	19	0	0
T10	0	18	0	0
T11	0	2	0	0
T12	12326	0	0	0
T13	3687	0	0	0
T14	5892	0	0	0
T15	3695	0	0	0
T16	2367	0	0	0
T17	24738	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664574719	663955259	0	0
T1	412703	411187	0	0
T2	21978	21891	0	0
T3	9263	9178	0	0
T8	41643	41556	0	0
T12	12326	12270	0	0
T13	3687	3617	0	0
T14	5892	5793	0	0
T15	3695	3600	0	0
T16	2367	2305	0	0
T17	24738	24682	0	0