Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 328643 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 4328744 1 T1 159 T2 152047 T3 11



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1156988 1 T1 54 T2 40549 T3 2
values[0x0] 1648784 1 T1 95 T2 57774 T3 7
values[0x1] 1851615 1 T1 100 T2 64854 T3 9



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 149793 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 4507594 1 T1 176 T2 158267 T3 11



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 19623 1 T2 659 T4 315 T10 2
valid_sources[0x01] 18141 1 T2 672 T4 380 T11 593
valid_sources[0x02] 18038 1 T1 1 T2 658 T4 322
valid_sources[0x03] 18463 1 T2 664 T4 377 T11 626
valid_sources[0x04] 18289 1 T1 3 T2 643 T4 414
valid_sources[0x05] 17946 1 T2 648 T4 390 T6 1
valid_sources[0x06] 18251 1 T2 660 T4 334 T10 2
valid_sources[0x07] 17820 1 T2 624 T4 370 T10 1
valid_sources[0x08] 18037 1 T1 1 T2 641 T4 366
valid_sources[0x09] 18301 1 T1 1 T2 600 T4 351
valid_sources[0x0a] 18836 1 T1 2 T2 641 T4 362
valid_sources[0x0b] 18645 1 T1 2 T2 679 T4 364
valid_sources[0x0c] 18944 1 T2 617 T4 381 T11 593
valid_sources[0x0d] 19439 1 T2 692 T4 362 T11 636
valid_sources[0x0e] 18465 1 T1 1 T2 635 T4 346
valid_sources[0x0f] 18209 1 T1 1 T2 608 T4 372
valid_sources[0x10] 18446 1 T2 670 T4 364 T11 602
valid_sources[0x11] 17760 1 T1 2 T2 620 T3 1
valid_sources[0x12] 18953 1 T2 619 T4 373 T10 2
valid_sources[0x13] 18572 1 T1 2 T2 695 T3 1
valid_sources[0x14] 18226 1 T1 1 T2 626 T4 384
valid_sources[0x15] 17652 1 T2 603 T4 377 T11 673
valid_sources[0x16] 17360 1 T1 2 T2 639 T4 373
valid_sources[0x17] 18425 1 T2 643 T4 366 T10 3
valid_sources[0x18] 17128 1 T2 650 T4 350 T10 1
valid_sources[0x19] 17468 1 T1 1 T2 662 T4 395
valid_sources[0x1a] 17598 1 T2 641 T4 379 T10 1
valid_sources[0x1b] 18252 1 T2 641 T4 370 T10 2
valid_sources[0x1c] 17322 1 T1 1 T2 677 T4 336
valid_sources[0x1d] 18415 1 T2 673 T3 1 T4 338
valid_sources[0x1e] 18141 1 T2 646 T4 364 T11 621
valid_sources[0x1f] 16695 1 T1 1 T2 643 T4 333
valid_sources[0x20] 17620 1 T1 1 T2 667 T4 366
valid_sources[0x21] 18993 1 T1 1 T2 662 T4 333
valid_sources[0x22] 17378 1 T1 1 T2 642 T4 385
valid_sources[0x23] 18066 1 T1 1 T2 682 T4 351
valid_sources[0x24] 18224 1 T2 670 T4 367 T10 2
valid_sources[0x25] 18225 1 T2 614 T3 1 T4 312
valid_sources[0x26] 18504 1 T2 645 T4 381 T7 1
valid_sources[0x27] 17925 1 T1 2 T2 658 T4 360
valid_sources[0x28] 17715 1 T1 1 T2 667 T4 358
valid_sources[0x29] 17756 1 T2 617 T4 388 T10 3
valid_sources[0x2a] 17476 1 T1 1 T2 615 T4 366
valid_sources[0x2b] 17550 1 T2 656 T4 369 T10 3
valid_sources[0x2c] 17923 1 T1 1 T2 608 T4 367
valid_sources[0x2d] 18727 1 T1 3 T2 639 T4 370
valid_sources[0x2e] 18379 1 T1 1 T2 602 T4 369
valid_sources[0x2f] 17520 1 T2 655 T4 356 T10 2
valid_sources[0x30] 17615 1 T2 700 T4 359 T11 652
valid_sources[0x31] 18509 1 T2 660 T4 385 T10 1
valid_sources[0x32] 18672 1 T1 2 T2 640 T4 329
valid_sources[0x33] 19051 1 T1 1 T2 652 T4 372
valid_sources[0x34] 17023 1 T1 1 T2 640 T4 362
valid_sources[0x35] 18582 1 T1 1 T2 651 T4 362
valid_sources[0x36] 17912 1 T1 1 T2 641 T4 382
valid_sources[0x37] 17621 1 T2 674 T4 376 T11 610
valid_sources[0x38] 19306 1 T1 2 T2 678 T4 383
valid_sources[0x39] 18720 1 T1 1 T2 603 T4 344
valid_sources[0x3a] 16992 1 T1 1 T2 644 T4 364
valid_sources[0x3b] 17794 1 T1 1 T2 656 T4 363
valid_sources[0x3c] 17576 1 T1 3 T2 623 T4 372
valid_sources[0x3d] 19407 1 T1 1 T2 643 T4 356
valid_sources[0x3e] 17915 1 T1 2 T2 644 T4 366
valid_sources[0x3f] 17724 1 T2 614 T4 380 T7 2
valid_sources[0x40] 18982 1 T1 2 T2 661 T4 370
valid_sources[0x41] 18199 1 T2 601 T4 332 T10 4
valid_sources[0x42] 18301 1 T2 640 T4 315 T10 1
valid_sources[0x43] 18067 1 T1 1 T2 604 T4 392
valid_sources[0x44] 18933 1 T1 1 T2 618 T4 395
valid_sources[0x45] 17445 1 T1 2 T2 587 T4 354
valid_sources[0x46] 17535 1 T2 593 T4 389 T7 1
valid_sources[0x47] 17521 1 T2 665 T4 365 T11 529
valid_sources[0x48] 18181 1 T1 1 T2 688 T4 386
valid_sources[0x49] 17714 1 T1 1 T2 640 T4 367
valid_sources[0x4a] 19473 1 T2 648 T4 336 T6 1
valid_sources[0x4b] 18444 1 T2 600 T4 355 T10 1
valid_sources[0x4c] 16995 1 T1 1 T2 631 T4 351
valid_sources[0x4d] 16973 1 T2 624 T4 383 T11 707
valid_sources[0x4e] 18833 1 T2 624 T4 380 T10 1
valid_sources[0x4f] 17860 1 T1 1 T2 693 T4 389
valid_sources[0x50] 17599 1 T1 2 T2 666 T4 366
valid_sources[0x51] 18518 1 T2 593 T4 395 T10 1
valid_sources[0x52] 17711 1 T1 2 T2 653 T4 380
valid_sources[0x53] 17244 1 T1 2 T2 624 T4 354
valid_sources[0x54] 17495 1 T1 4 T2 682 T4 316
valid_sources[0x55] 18213 1 T1 2 T2 657 T4 352
valid_sources[0x56] 17015 1 T1 1 T2 636 T4 397
valid_sources[0x57] 17966 1 T1 1 T2 653 T4 351
valid_sources[0x58] 19260 1 T2 635 T4 379 T10 5
valid_sources[0x59] 17387 1 T1 2 T2 624 T4 354
valid_sources[0x5a] 18275 1 T1 2 T2 630 T4 388
valid_sources[0x5b] 17626 1 T2 625 T4 419 T10 2
valid_sources[0x5c] 19571 1 T1 3 T2 613 T4 354
valid_sources[0x5d] 19099 1 T2 599 T4 328 T10 1
valid_sources[0x5e] 18405 1 T2 558 T3 1 T4 353
valid_sources[0x5f] 17252 1 T2 605 T4 380 T9 1
valid_sources[0x60] 17906 1 T1 1 T2 616 T3 1
valid_sources[0x61] 18368 1 T1 1 T2 634 T4 339
valid_sources[0x62] 17026 1 T2 649 T4 343 T10 1
valid_sources[0x63] 17441 1 T1 2 T2 703 T4 338
valid_sources[0x64] 18097 1 T2 604 T4 336 T10 1
valid_sources[0x65] 18565 1 T1 1 T2 637 T4 351
valid_sources[0x66] 17878 1 T2 606 T4 385 T10 1
valid_sources[0x67] 16280 1 T2 615 T4 380 T11 655
valid_sources[0x68] 19648 1 T2 569 T4 352 T10 1
valid_sources[0x69] 17771 1 T1 1 T2 581 T4 343
valid_sources[0x6a] 16538 1 T2 608 T3 1 T4 346
valid_sources[0x6b] 18627 1 T1 3 T2 681 T4 332
valid_sources[0x6c] 18946 1 T1 2 T2 649 T4 417
valid_sources[0x6d] 18686 1 T1 1 T2 633 T4 369
valid_sources[0x6e] 18107 1 T1 1 T2 626 T4 366
valid_sources[0x6f] 19049 1 T1 2 T2 663 T4 364
valid_sources[0x70] 17441 1 T1 1 T2 643 T4 354
valid_sources[0x71] 18427 1 T1 2 T2 621 T4 414
valid_sources[0x72] 18294 1 T2 669 T4 390 T10 2
valid_sources[0x73] 18821 1 T2 659 T4 374 T10 1
valid_sources[0x74] 18170 1 T2 644 T4 375 T11 641
valid_sources[0x75] 17552 1 T1 3 T2 642 T4 362
valid_sources[0x76] 18298 1 T2 624 T4 370 T10 1
valid_sources[0x77] 18972 1 T2 679 T4 369 T11 612
valid_sources[0x78] 17731 1 T2 626 T4 367 T11 598
valid_sources[0x79] 18137 1 T1 1 T2 584 T4 385
valid_sources[0x7a] 16786 1 T1 3 T2 661 T3 1
valid_sources[0x7b] 18559 1 T2 648 T4 387 T11 604
valid_sources[0x7c] 17226 1 T1 2 T2 666 T4 345
valid_sources[0x7d] 18165 1 T1 2 T2 644 T3 1
valid_sources[0x7e] 17172 1 T2 590 T4 392 T10 5
valid_sources[0x7f] 16971 1 T2 637 T4 350 T7 2
valid_sources[0x80] 19752 1 T1 2 T2 666 T4 357



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 1083889 1 T1 30 T2 38124 T3 1
values[0x0] all_enables biggest_size 1621627 1 T1 65 T2 57028 T3 4
values[0x1] all_enables biggest_size 1623228 1 T1 64 T2 56895 T3 6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%