Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	711643395	6214714	0	0
wdog_bark_thold_rd_A	711643395	118734	0	0
wdog_bite_thold_rd_A	711643395	105671	0	0
wdog_ctrl_rd_A	711643395	104693	0	0
wdog_regwen_rd_A	711643395	120732	0	0
wkup_ctrl_rd_A	711643395	104379	0	0
wkup_thold_rd_A	711643395	118495	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711643395	6214714	0	0
T2	502101	222045	0	0
T3	10202	0	0	0
T4	424956	125151	0	0
T5	9560	0	0	0
T6	25059	0	0	0
T7	156736	0	0	0
T8	153238	0	0	0
T9	165874	0	0	0
T10	209634	0	0	0
T11	783894	212334	0	0
T23	0	92900	0	0
T24	0	145041	0	0
T26	0	191950	0	0
T31	0	159909	0	0
T32	0	44541	0	0
T38	0	33201	0	0
T39	0	119990	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711643395	118734	0	0
T4	424956	5599	0	0
T5	9560	0	0	0
T6	25059	0	0	0
T7	156736	0	0	0
T8	153238	0	0	0
T9	165874	0	0	0
T10	209634	0	0	0
T11	783894	17679	0	0
T12	5091	0	0	0
T24	0	12418	0	0
T30	23232	0	0	0
T81	0	4839	0	0
T82	0	6043	0	0
T83	0	4194	0	0
T84	0	3408	0	0
T85	0	6784	0	0
T86	0	19938	0	0
T87	0	29310	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711643395	105671	0	0
T4	424956	4903	0	0
T5	9560	0	0	0
T6	25059	0	0	0
T7	156736	0	0	0
T8	153238	0	0	0
T9	165874	0	0	0
T10	209634	0	0	0
T11	783894	15007	0	0
T12	5091	0	0	0
T24	0	11168	0	0
T30	23232	0	0	0
T81	0	4431	0	0
T82	0	5507	0	0
T83	0	3837	0	0
T84	0	2883	0	0
T85	0	6217	0	0
T86	0	17353	0	0
T87	0	26545	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711643395	104693	0	0
T4	424956	5061	0	0
T5	9560	0	0	0
T6	25059	0	0	0
T7	156736	0	0	0
T8	153238	0	0	0
T9	165874	0	0	0
T10	209634	0	0	0
T11	783894	15423	0	0
T12	5091	0	0	0
T24	0	10827	0	0
T30	23232	0	0	0
T81	0	3819	0	0
T82	0	5669	0	0
T83	0	3531	0	0
T84	0	3025	0	0
T85	0	6039	0	0
T86	0	17782	0	0
T87	0	25450	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711643395	120732	0	0
T4	424956	5699	0	0
T5	9560	0	0	0
T6	25059	0	0	0
T7	156736	0	0	0
T8	153238	0	0	0
T9	165874	0	0	0
T10	209634	0	0	0
T11	783894	17678	0	0
T12	5091	0	0	0
T24	0	12243	0	0
T30	23232	0	0	0
T81	0	4520	0	0
T82	0	5962	0	0
T83	0	4272	0	0
T84	0	3655	0	0
T85	0	6689	0	0
T86	0	20751	0	0
T87	0	29638	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711643395	104379	0	0
T4	424956	5073	0	0
T5	9560	0	0	0
T6	25059	0	0	0
T7	156736	0	0	0
T8	153238	0	0	0
T9	165874	0	0	0
T10	209634	0	0	0
T11	783894	15420	0	0
T12	5091	0	0	0
T24	0	11076	0	0
T30	23232	0	0	0
T81	0	4312	0	0
T82	0	5002	0	0
T83	0	3560	0	0
T84	0	3125	0	0
T85	0	6013	0	0
T86	0	17121	0	0
T87	0	25496	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711643395	118495	0	0
T4	424956	5608	0	0
T5	9560	0	0	0
T6	25059	0	0	0
T7	156736	0	0	0
T8	153238	0	0	0
T9	165874	0	0	0
T10	209634	0	0	0
T11	783894	17749	0	0
T12	5091	0	0	0
T24	0	12519	0	0
T30	23232	0	0	0
T81	0	4666	0	0
T82	0	5786	0	0
T83	0	4240	0	0
T84	0	3450	0	0
T85	0	6495	0	0
T86	0	19374	0	0
T87	0	29523	0	0