Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	376180	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5012476	1		T1	8		T2	11		T3	189

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1336373	1		T1	2		T2	2		T4	1
values[0x0]	1911019	1		T1	12		T2	6		T3	122
values[0x1]	2141264	1		T1	3		T2	10		T3	119

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	170397	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5218259	1		T1	8		T2	12		T3	211

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21786	1		T5	919		T10	401		T15	1
valid_sources[0x01]	20586	1		T5	85		T7	3		T8	1
valid_sources[0x02]	20545	1		T5	609		T10	422		T15	97
valid_sources[0x03]	21191	1		T5	657		T7	2		T10	407
valid_sources[0x04]	20953	1		T5	1128		T10	393		T15	90
valid_sources[0x05]	21889	1		T5	907		T10	435		T11	2
valid_sources[0x06]	20865	1		T5	746		T7	1		T10	453
valid_sources[0x07]	20171	1		T5	394		T10	406		T15	9
valid_sources[0x08]	21706	1		T1	1		T5	695		T10	427
valid_sources[0x09]	20535	1		T2	1		T5	837		T7	3
valid_sources[0x0a]	19519	1		T5	190		T8	1		T10	425
valid_sources[0x0b]	21279	1		T5	808		T7	1		T8	1
valid_sources[0x0c]	21805	1		T5	236		T7	1		T10	446
valid_sources[0x0d]	21738	1		T5	666		T7	2		T10	435
valid_sources[0x0e]	19442	1		T5	437		T7	1		T10	433
valid_sources[0x0f]	21149	1		T5	737		T7	1		T9	334
valid_sources[0x10]	20204	1		T5	548		T7	1		T10	434
valid_sources[0x11]	21154	1		T5	424		T7	1		T10	419
valid_sources[0x12]	19900	1		T5	728		T10	434		T15	119
valid_sources[0x13]	20192	1		T5	492		T10	425		T21	389
valid_sources[0x14]	21922	1		T5	1064		T10	454		T15	291
valid_sources[0x15]	21388	1		T5	722		T7	1		T10	443
valid_sources[0x16]	20225	1		T5	438		T8	1		T10	445
valid_sources[0x17]	21473	1		T5	337		T10	442		T15	165
valid_sources[0x18]	20602	1		T5	366		T7	1		T10	486
valid_sources[0x19]	20311	1		T5	622		T7	4		T10	422
valid_sources[0x1a]	20624	1		T5	338		T7	2		T10	426
valid_sources[0x1b]	21676	1		T5	691		T7	1		T10	426
valid_sources[0x1c]	20743	1		T5	532		T7	1		T10	456
valid_sources[0x1d]	21061	1		T5	626		T7	1		T10	444
valid_sources[0x1e]	21540	1		T5	820		T7	2		T10	387
valid_sources[0x1f]	20789	1		T5	164		T6	1		T10	427
valid_sources[0x20]	21732	1		T2	1		T5	876		T10	418
valid_sources[0x21]	21786	1		T5	509		T7	2		T10	411
valid_sources[0x22]	20506	1		T5	458		T7	1		T10	420
valid_sources[0x23]	22520	1		T5	434		T7	1		T10	410
valid_sources[0x24]	21699	1		T5	924		T10	415		T15	485
valid_sources[0x25]	20650	1		T5	443		T10	440		T21	680
valid_sources[0x26]	19520	1		T5	501		T7	1		T10	429
valid_sources[0x27]	20937	1		T5	650		T10	437		T15	60
valid_sources[0x28]	22037	1		T5	205		T10	416		T15	2
valid_sources[0x29]	20972	1		T5	303		T10	421		T13	1
valid_sources[0x2a]	21942	1		T5	850		T10	373		T12	18
valid_sources[0x2b]	20897	1		T5	937		T7	1		T10	416
valid_sources[0x2c]	20034	1		T5	325		T10	387		T15	43
valid_sources[0x2d]	20943	1		T5	897		T7	1		T10	471
valid_sources[0x2e]	21504	1		T5	786		T7	3		T10	369
valid_sources[0x2f]	22911	1		T5	937		T7	3		T10	441
valid_sources[0x30]	22202	1		T5	176		T7	1		T10	407
valid_sources[0x31]	22082	1		T5	915		T7	1		T10	396
valid_sources[0x32]	21212	1		T5	282		T7	4		T10	397
valid_sources[0x33]	20895	1		T1	1		T5	732		T10	479
valid_sources[0x34]	21528	1		T5	569		T7	1		T10	425
valid_sources[0x35]	21598	1		T5	402		T7	2		T10	474
valid_sources[0x36]	19521	1		T5	568		T7	1		T10	400
valid_sources[0x37]	22518	1		T1	1		T5	842		T7	4
valid_sources[0x38]	21194	1		T5	149		T7	1		T10	437
valid_sources[0x39]	21980	1		T5	934		T7	4		T10	388
valid_sources[0x3a]	22313	1		T5	601		T10	370		T14	1
valid_sources[0x3b]	20621	1		T5	179		T7	2		T10	444
valid_sources[0x3c]	20497	1		T5	841		T6	1		T10	447
valid_sources[0x3d]	22553	1		T5	542		T10	438		T21	656
valid_sources[0x3e]	20031	1		T5	423		T7	1		T10	417
valid_sources[0x3f]	20062	1		T5	657		T6	1		T7	1
valid_sources[0x40]	22347	1		T5	757		T7	2		T10	425
valid_sources[0x41]	20903	1		T5	675		T7	1		T10	434
valid_sources[0x42]	20320	1		T5	713		T7	2		T8	1
valid_sources[0x43]	21567	1		T5	1336		T7	2		T10	398
valid_sources[0x44]	20171	1		T5	332		T7	1		T10	428
valid_sources[0x45]	20297	1		T5	283		T7	2		T10	412
valid_sources[0x46]	21497	1		T5	736		T7	2		T10	429
valid_sources[0x47]	21427	1		T5	204		T7	1		T10	434
valid_sources[0x48]	21242	1		T5	581		T7	2		T10	405
valid_sources[0x49]	20608	1		T5	733		T7	2		T10	434
valid_sources[0x4a]	20372	1		T5	840		T6	1		T10	422
valid_sources[0x4b]	20615	1		T5	84		T10	409		T21	1249
valid_sources[0x4c]	20791	1		T5	358		T10	414		T15	10
valid_sources[0x4d]	22116	1		T5	1067		T7	3		T10	428
valid_sources[0x4e]	20546	1		T2	1		T5	527		T7	1
valid_sources[0x4f]	21136	1		T5	1111		T7	1		T10	439
valid_sources[0x50]	21618	1		T5	495		T10	436		T15	100
valid_sources[0x51]	21302	1		T5	662		T6	1		T7	1
valid_sources[0x52]	21603	1		T5	296		T7	1		T10	430
valid_sources[0x53]	20298	1		T1	1		T5	370		T7	1
valid_sources[0x54]	20349	1		T2	1		T5	335		T10	441
valid_sources[0x55]	20367	1		T5	229		T7	4		T10	418
valid_sources[0x56]	19999	1		T5	139		T10	434		T21	314
valid_sources[0x57]	21504	1		T5	624		T7	1		T10	452
valid_sources[0x58]	21088	1		T5	653		T10	439		T15	38
valid_sources[0x59]	20659	1		T5	317		T10	467		T15	106
valid_sources[0x5a]	20274	1		T2	1		T5	857		T7	4
valid_sources[0x5b]	21328	1		T2	1		T5	548		T7	1
valid_sources[0x5c]	20102	1		T3	301		T5	532		T7	5
valid_sources[0x5d]	20853	1		T5	375		T10	417		T21	774
valid_sources[0x5e]	20105	1		T5	530		T7	1		T10	467
valid_sources[0x5f]	20171	1		T5	713		T7	1		T10	416
valid_sources[0x60]	20660	1		T5	367		T7	4		T10	473
valid_sources[0x61]	21728	1		T5	865		T7	1		T10	451
valid_sources[0x62]	21062	1		T5	649		T7	2		T10	388
valid_sources[0x63]	21268	1		T5	784		T10	445		T14	2
valid_sources[0x64]	20035	1		T5	731		T6	1		T7	2
valid_sources[0x65]	20573	1		T5	456		T10	429		T15	2
valid_sources[0x66]	20748	1		T5	972		T10	415		T15	7
valid_sources[0x67]	21251	1		T2	1		T5	394		T10	421
valid_sources[0x68]	20787	1		T5	505		T7	1		T10	450
valid_sources[0x69]	20878	1		T5	455		T7	2		T10	394
valid_sources[0x6a]	20648	1		T5	449		T10	463		T15	295
valid_sources[0x6b]	22940	1		T5	783		T10	462		T15	5
valid_sources[0x6c]	21154	1		T5	774		T7	3		T10	417
valid_sources[0x6d]	19942	1		T5	539		T7	3		T10	390
valid_sources[0x6e]	21662	1		T5	656		T7	1		T10	416
valid_sources[0x6f]	21608	1		T5	546		T6	1		T7	1
valid_sources[0x70]	20022	1		T2	1		T5	456		T10	452
valid_sources[0x71]	22417	1		T5	1079		T7	2		T10	390
valid_sources[0x72]	19743	1		T5	571		T10	388		T21	307
valid_sources[0x73]	21787	1		T5	958		T7	2		T10	407
valid_sources[0x74]	21044	1		T5	742		T7	4		T10	402
valid_sources[0x75]	22314	1		T1	1		T5	366		T7	2
valid_sources[0x76]	21107	1		T5	381		T10	399		T15	104
valid_sources[0x77]	20691	1		T5	474		T7	2		T8	1
valid_sources[0x78]	22378	1		T5	821		T7	2		T10	432
valid_sources[0x79]	20151	1		T5	267		T7	1		T10	451
valid_sources[0x7a]	20688	1		T5	566		T7	4		T10	432
valid_sources[0x7b]	21282	1		T1	1		T5	552		T7	1
valid_sources[0x7c]	21431	1		T5	595		T10	433		T15	142
valid_sources[0x7d]	19542	1		T5	678		T7	2		T10	473
valid_sources[0x7e]	21755	1		T5	854		T7	1		T10	411
valid_sources[0x7f]	20786	1		T5	810		T7	2		T10	409
valid_sources[0x80]	19537	1		T5	794		T10	418		T15	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1253147

1

T2

1

T3

28

T5

35955

values[0x0]

all_enables

biggest_size

1880161

1

T1

6

T2

5

T3

85

values[0x1]

all_enables

biggest_size

1879168

1

T1

2

T2

5

T3

76