Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	686297960	7150616	0	0
wdog_bark_thold_rd_A	686297960	157000	0	0
wdog_bite_thold_rd_A	686297960	136035	0	0
wdog_ctrl_rd_A	686297960	138978	0	0
wdog_regwen_rd_A	686297960	157396	0	0
wkup_ctrl_rd_A	686297960	137090	0	0
wkup_thold_rd_A	686297960	158620	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686297960	7150616	0	0
T5	741366	197875	0	0
T6	935313	0	0	0
T7	109562	0	0	0
T8	55735	0	0	0
T9	879954	0	0	0
T10	345499	151986	0	0
T11	159606	0	0	0
T12	21871	0	0	0
T13	9959	0	0	0
T14	57625	0	0	0
T15	0	35175	0	0
T21	0	146016	0	0
T22	0	101966	0	0
T32	0	458455	0	0
T33	0	166043	0	0
T34	0	70145	0	0
T35	0	54430	0	0
T36	0	62008	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686297960	157000	0	0
T5	741366	16244	0	0
T6	935313	0	0	0
T7	109562	0	0	0
T8	55735	0	0	0
T9	879954	0	0	0
T10	345499	0	0	0
T11	159606	0	0	0
T12	21871	0	0	0
T13	9959	0	0	0
T14	57625	0	0	0
T22	0	8382	0	0
T34	0	6391	0	0
T36	0	2711	0	0
T74	0	19095	0	0
T75	0	19468	0	0
T76	0	2371	0	0
T77	0	3845	0	0
T78	0	10616	0	0
T79	0	5080	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686297960	136035	0	0
T5	741366	13913	0	0
T6	935313	0	0	0
T7	109562	0	0	0
T8	55735	0	0	0
T9	879954	0	0	0
T10	345499	0	0	0
T11	159606	0	0	0
T12	21871	0	0	0
T13	9959	0	0	0
T14	57625	0	0	0
T22	0	7509	0	0
T34	0	5389	0	0
T36	0	2584	0	0
T74	0	16441	0	0
T75	0	17380	0	0
T76	0	1824	0	0
T77	0	3544	0	0
T78	0	9073	0	0
T79	0	4159	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686297960	138978	0	0
T5	741366	13915	0	0
T6	935313	0	0	0
T7	109562	0	0	0
T8	55735	0	0	0
T9	879954	0	0	0
T10	345499	0	0	0
T11	159606	0	0	0
T12	21871	0	0	0
T13	9959	0	0	0
T14	57625	0	0	0
T22	0	7509	0	0
T34	0	5505	0	0
T36	0	2341	0	0
T74	0	17301	0	0
T75	0	17348	0	0
T76	0	1917	0	0
T77	0	3402	0	0
T78	0	9143	0	0
T79	0	4365	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686297960	157396	0	0
T5	741366	16352	0	0
T6	935313	0	0	0
T7	109562	0	0	0
T8	55735	0	0	0
T9	879954	0	0	0
T10	345499	0	0	0
T11	159606	0	0	0
T12	21871	0	0	0
T13	9959	0	0	0
T14	57625	0	0	0
T22	0	8667	0	0
T34	0	5867	0	0
T36	0	2528	0	0
T74	0	19378	0	0
T75	0	19777	0	0
T76	0	2318	0	0
T77	0	3843	0	0
T78	0	10528	0	0
T79	0	4845	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686297960	137090	0	0
T5	741366	13626	0	0
T6	935313	0	0	0
T7	109562	0	0	0
T8	55735	0	0	0
T9	879954	0	0	0
T10	345499	0	0	0
T11	159606	0	0	0
T12	21871	0	0	0
T13	9959	0	0	0
T14	57625	0	0	0
T22	0	7628	0	0
T34	0	5235	0	0
T36	0	2276	0	0
T74	0	17005	0	0
T75	0	17302	0	0
T76	0	1935	0	0
T77	0	3578	0	0
T78	0	8842	0	0
T79	0	4078	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686297960	158620	0	0
T5	741366	16528	0	0
T6	935313	0	0	0
T7	109562	0	0	0
T8	55735	0	0	0
T9	879954	0	0	0
T10	345499	0	0	0
T11	159606	0	0	0
T12	21871	0	0	0
T13	9959	0	0	0
T14	57625	0	0	0
T22	0	8733	0	0
T34	0	6372	0	0
T36	0	2820	0	0
T74	0	19296	0	0
T75	0	19694	0	0
T76	0	2355	0	0
T77	0	3850	0	0
T78	0	10258	0	0
T79	0	5059	0	0