Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	388984	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5181369	1		T1	10		T2	15		T3	10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1380976	1		T1	2		T2	3		T3	2
values[0x0]	1976539	1		T1	10		T2	8		T3	10
values[0x1]	2212838	1		T1	4		T2	9		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	176529	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5393824	1		T1	10		T2	15		T3	10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21568	1		T4	466		T6	189		T15	753
valid_sources[0x01]	21997	1		T4	462		T6	530		T11	1
valid_sources[0x02]	20494	1		T4	476		T6	449		T15	751
valid_sources[0x03]	21901	1		T4	422		T6	103		T11	1
valid_sources[0x04]	21216	1		T4	470		T6	685		T15	692
valid_sources[0x05]	22931	1		T4	478		T6	491		T15	753
valid_sources[0x06]	21144	1		T4	498		T6	128		T15	705
valid_sources[0x07]	23727	1		T4	459		T6	558		T15	704
valid_sources[0x08]	22103	1		T1	2		T4	442		T6	698
valid_sources[0x09]	21941	1		T4	525		T6	745		T15	686
valid_sources[0x0a]	21113	1		T4	507		T6	611		T15	726
valid_sources[0x0b]	21319	1		T2	1		T4	452		T6	85
valid_sources[0x0c]	20281	1		T4	490		T5	1		T6	119
valid_sources[0x0d]	23566	1		T4	491		T6	385		T11	7
valid_sources[0x0e]	21176	1		T4	458		T6	534		T15	679
valid_sources[0x0f]	22503	1		T4	495		T6	306		T15	704
valid_sources[0x10]	21453	1		T4	486		T6	507		T15	708
valid_sources[0x11]	22356	1		T4	483		T6	104		T15	729
valid_sources[0x12]	21616	1		T4	486		T6	913		T11	1
valid_sources[0x13]	21956	1		T4	464		T6	311		T15	736
valid_sources[0x14]	22545	1		T4	483		T6	477		T15	765
valid_sources[0x15]	20428	1		T4	476		T6	274		T11	3
valid_sources[0x16]	19304	1		T4	493		T6	368		T15	695
valid_sources[0x17]	22481	1		T4	477		T6	203		T12	2
valid_sources[0x18]	21306	1		T4	451		T6	509		T11	1
valid_sources[0x19]	21830	1		T4	476		T6	130		T11	7
valid_sources[0x1a]	22220	1		T4	434		T6	814		T11	1
valid_sources[0x1b]	20385	1		T4	438		T6	198		T11	1
valid_sources[0x1c]	21828	1		T4	491		T6	369		T11	2
valid_sources[0x1d]	22226	1		T4	402		T6	480		T15	758
valid_sources[0x1e]	20873	1		T4	454		T6	510		T15	735
valid_sources[0x1f]	23114	1		T4	442		T6	651		T15	737
valid_sources[0x20]	21915	1		T4	497		T6	237		T11	5
valid_sources[0x21]	21624	1		T4	459		T6	524		T11	1
valid_sources[0x22]	20201	1		T4	452		T6	467		T11	1
valid_sources[0x23]	20920	1		T4	456		T6	461		T9	1
valid_sources[0x24]	22486	1		T4	467		T6	660		T15	755
valid_sources[0x25]	21993	1		T2	1		T4	509		T6	714
valid_sources[0x26]	21564	1		T4	475		T6	477		T11	2
valid_sources[0x27]	22306	1		T4	468		T6	519		T15	705
valid_sources[0x28]	22506	1		T4	470		T5	1		T6	629
valid_sources[0x29]	22178	1		T4	465		T6	351		T15	757
valid_sources[0x2a]	23974	1		T4	480		T6	943		T11	2
valid_sources[0x2b]	21251	1		T4	478		T6	369		T9	2
valid_sources[0x2c]	21971	1		T4	462		T6	632		T15	691
valid_sources[0x2d]	21908	1		T4	474		T6	300		T15	674
valid_sources[0x2e]	20653	1		T4	442		T6	613		T11	2
valid_sources[0x2f]	21252	1		T2	1		T4	479		T6	400
valid_sources[0x30]	21834	1		T4	480		T6	679		T13	8
valid_sources[0x31]	21284	1		T4	443		T5	2		T6	485
valid_sources[0x32]	22395	1		T4	434		T6	941		T11	1
valid_sources[0x33]	22245	1		T4	455		T6	291		T15	741
valid_sources[0x34]	23492	1		T4	478		T6	858		T15	681
valid_sources[0x35]	20810	1		T4	447		T6	118		T11	1
valid_sources[0x36]	22322	1		T4	448		T6	188		T11	1
valid_sources[0x37]	22050	1		T4	513		T6	386		T15	780
valid_sources[0x38]	23125	1		T4	457		T6	841		T11	1
valid_sources[0x39]	22637	1		T4	453		T6	260		T15	709
valid_sources[0x3a]	22405	1		T4	451		T6	566		T11	6
valid_sources[0x3b]	22330	1		T4	474		T6	372		T9	2
valid_sources[0x3c]	22617	1		T4	494		T6	473		T15	744
valid_sources[0x3d]	21706	1		T4	457		T6	668		T9	1
valid_sources[0x3e]	20946	1		T4	480		T6	422		T15	754
valid_sources[0x3f]	22772	1		T4	474		T6	506		T15	795
valid_sources[0x40]	21974	1		T4	504		T6	37		T11	2
valid_sources[0x41]	21326	1		T4	465		T6	130		T9	1
valid_sources[0x42]	20775	1		T4	455		T5	2		T6	172
valid_sources[0x43]	21797	1		T4	472		T6	387		T8	1
valid_sources[0x44]	21796	1		T4	481		T6	336		T15	739
valid_sources[0x45]	21590	1		T2	1		T4	493		T6	1009
valid_sources[0x46]	21886	1		T4	441		T6	671		T15	732
valid_sources[0x47]	21616	1		T4	457		T6	303		T11	1
valid_sources[0x48]	21726	1		T4	427		T6	648		T11	1
valid_sources[0x49]	21699	1		T4	484		T6	126		T15	716
valid_sources[0x4a]	21312	1		T4	461		T6	363		T11	6
valid_sources[0x4b]	21044	1		T4	487		T6	175		T15	741
valid_sources[0x4c]	22034	1		T4	469		T6	575		T9	1
valid_sources[0x4d]	22295	1		T4	459		T6	626		T11	1
valid_sources[0x4e]	22767	1		T4	479		T6	154		T15	744
valid_sources[0x4f]	21046	1		T4	506		T6	114		T15	758
valid_sources[0x50]	20429	1		T4	459		T6	541		T11	1
valid_sources[0x51]	20569	1		T4	478		T6	382		T15	717
valid_sources[0x52]	21324	1		T2	1		T4	473		T6	463
valid_sources[0x53]	21711	1		T4	443		T6	458		T15	749
valid_sources[0x54]	21887	1		T4	495		T6	895		T15	726
valid_sources[0x55]	21272	1		T4	476		T6	182		T11	3
valid_sources[0x56]	22013	1		T4	456		T6	336		T11	2
valid_sources[0x57]	23522	1		T4	525		T6	521		T11	3
valid_sources[0x58]	21879	1		T1	1		T4	459		T6	143
valid_sources[0x59]	21683	1		T4	460		T6	452		T15	775
valid_sources[0x5a]	21619	1		T4	490		T6	838		T15	722
valid_sources[0x5b]	22078	1		T4	477		T6	695		T15	746
valid_sources[0x5c]	22303	1		T4	473		T6	486		T15	809
valid_sources[0x5d]	22521	1		T2	1		T4	435		T6	645
valid_sources[0x5e]	22897	1		T4	515		T6	247		T11	1
valid_sources[0x5f]	21435	1		T4	472		T6	231		T15	671
valid_sources[0x60]	20404	1		T4	461		T6	322		T15	707
valid_sources[0x61]	22380	1		T4	491		T6	681		T11	1
valid_sources[0x62]	22202	1		T4	497		T6	509		T15	748
valid_sources[0x63]	21921	1		T4	530		T6	558		T15	736
valid_sources[0x64]	20794	1		T4	492		T6	149		T9	1
valid_sources[0x65]	20713	1		T4	477		T6	294		T9	1
valid_sources[0x66]	22227	1		T4	517		T6	40		T11	1
valid_sources[0x67]	19918	1		T4	514		T6	263		T11	2
valid_sources[0x68]	21447	1		T4	444		T6	549		T15	742
valid_sources[0x69]	20994	1		T4	459		T6	387		T7	17
valid_sources[0x6a]	21145	1		T4	480		T6	760		T11	4
valid_sources[0x6b]	22966	1		T2	2		T4	457		T6	302
valid_sources[0x6c]	20779	1		T4	449		T6	171		T15	734
valid_sources[0x6d]	22826	1		T2	1		T4	453		T6	743
valid_sources[0x6e]	22186	1		T4	452		T6	538		T15	771
valid_sources[0x6f]	21605	1		T4	493		T6	470		T15	689
valid_sources[0x70]	23010	1		T2	1		T4	453		T6	312
valid_sources[0x71]	23494	1		T4	479		T6	745		T11	1
valid_sources[0x72]	22289	1		T4	453		T6	458		T11	1
valid_sources[0x73]	19719	1		T4	436		T6	14		T15	751
valid_sources[0x74]	20299	1		T2	1		T4	415		T6	180
valid_sources[0x75]	20775	1		T4	514		T6	266		T15	790
valid_sources[0x76]	22071	1		T4	462		T6	497		T15	734
valid_sources[0x77]	20789	1		T4	491		T6	667		T15	798
valid_sources[0x78]	21808	1		T4	450		T6	208		T11	6
valid_sources[0x79]	20250	1		T4	418		T6	420		T10	3
valid_sources[0x7a]	20872	1		T4	475		T6	358		T11	2
valid_sources[0x7b]	23024	1		T1	1		T4	491		T5	1
valid_sources[0x7c]	21881	1		T4	498		T6	631		T8	7
valid_sources[0x7d]	20627	1		T4	482		T6	365		T9	1
valid_sources[0x7e]	23730	1		T4	481		T6	223		T11	1
valid_sources[0x7f]	22442	1		T4	473		T5	1		T6	715
valid_sources[0x80]	23721	1		T4	471		T6	786		T15	665

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1294626

1

T1

1

T2

3

T3

1

values[0x0]

all_enables

biggest_size

1944941

1

T1

7

T2

6

T3

6

values[0x1]

all_enables

biggest_size

1941802

1

T1

2

T2

6

T3

3