Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	720815656	7414214	0	0
wdog_bark_thold_rd_A	720815656	126343	0	0
wdog_bite_thold_rd_A	720815656	110418	0	0
wdog_ctrl_rd_A	720815656	110063	0	0
wdog_regwen_rd_A	720815656	126739	0	0
wkup_ctrl_rd_A	720815656	110684	0	0
wkup_thold_rd_A	720815656	126674	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720815656	7414214	0	0
T4	475809	153802	0	0
T5	23668	0	0	0
T6	345758	144731	0	0
T7	292243	0	0	0
T8	36050	0	0	0
T9	653497	0	0	0
T10	36416	0	0	0
T11	849110	0	0	0
T12	506095	0	0	0
T13	54355	0	0	0
T15	0	255119	0	0
T17	0	146478	0	0
T26	0	327659	0	0
T36	0	108055	0	0
T45	0	249613	0	0
T46	0	62266	0	0
T47	0	154819	0	0
T48	0	109964	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720815656	126343	0	0
T22	779292	0	0	0
T36	354993	4678	0	0
T45	560096	0	0	0
T46	0	5241	0	0
T51	322082	0	0	0
T52	557653	0	0	0
T53	8393	0	0	0
T92	0	8941	0	0
T97	0	17600	0	0
T98	0	14876	0	0
T99	0	6131	0	0
T100	0	6058	0	0
T101	0	14224	0	0
T102	0	9535	0	0
T103	0	6463	0	0
T104	15425	0	0	0
T105	201635	0	0	0
T106	243554	0	0	0
T107	13775	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720815656	110418	0	0
T22	779292	0	0	0
T36	354993	4211	0	0
T45	560096	0	0	0
T46	0	4699	0	0
T51	322082	0	0	0
T52	557653	0	0	0
T53	8393	0	0	0
T92	0	7705	0	0
T97	0	15341	0	0
T98	0	12962	0	0
T99	0	5337	0	0
T100	0	5139	0	0
T101	0	12730	0	0
T102	0	8432	0	0
T103	0	5745	0	0
T104	15425	0	0	0
T105	201635	0	0	0
T106	243554	0	0	0
T107	13775	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720815656	110063	0	0
T22	779292	0	0	0
T36	354993	4474	0	0
T45	560096	0	0	0
T46	0	4256	0	0
T51	322082	0	0	0
T52	557653	0	0	0
T53	8393	0	0	0
T92	0	7520	0	0
T97	0	15627	0	0
T98	0	13212	0	0
T99	0	5317	0	0
T100	0	4947	0	0
T101	0	12372	0	0
T102	0	8356	0	0
T103	0	5879	0	0
T104	15425	0	0	0
T105	201635	0	0	0
T106	243554	0	0	0
T107	13775	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720815656	126739	0	0
T22	779292	0	0	0
T36	354993	4767	0	0
T45	560096	0	0	0
T46	0	4838	0	0
T51	322082	0	0	0
T52	557653	0	0	0
T53	8393	0	0	0
T92	0	9063	0	0
T97	0	17289	0	0
T98	0	15193	0	0
T99	0	6225	0	0
T100	0	5684	0	0
T101	0	14386	0	0
T102	0	9634	0	0
T103	0	6449	0	0
T104	15425	0	0	0
T105	201635	0	0	0
T106	243554	0	0	0
T107	13775	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720815656	110684	0	0
T22	779292	0	0	0
T36	354993	4240	0	0
T45	560096	0	0	0
T46	0	4303	0	0
T51	322082	0	0	0
T52	557653	0	0	0
T53	8393	0	0	0
T92	0	7762	0	0
T97	0	15527	0	0
T98	0	13160	0	0
T99	0	5233	0	0
T100	0	4924	0	0
T101	0	12461	0	0
T102	0	8784	0	0
T103	0	5757	0	0
T104	15425	0	0	0
T105	201635	0	0	0
T106	243554	0	0	0
T107	13775	0	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	720815656	126674	0	0
T22	779292	0	0	0
T36	354993	4864	0	0
T45	560096	0	0	0
T46	0	5032	0	0
T51	322082	0	0	0
T52	557653	0	0	0
T53	8393	0	0	0
T92	0	8786	0	0
T97	0	17923	0	0
T98	0	15681	0	0
T99	0	6458	0	0
T100	0	5743	0	0
T101	0	14235	0	0
T102	0	9450	0	0
T103	0	6305	0	0
T104	15425	0	0	0
T105	201635	0	0	0
T106	243554	0	0	0
T107	13775	0	0	0