Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	432293	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5793406	1		T1	148		T2	12		T3	9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1544798	1		T1	54		T2	3		T3	2
values[0x0]	2204287	1		T1	100		T2	7		T3	7
values[0x1]	2476614	1		T1	85		T2	8		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	194170	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	6031529	1		T1	164		T2	12		T3	9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24813	1		T5	454		T8	1228		T9	9
valid_sources[0x01]	22994	1		T5	217		T8	1336		T9	1
valid_sources[0x02]	23919	1		T5	362		T8	881		T17	676
valid_sources[0x03]	26278	1		T5	213		T8	1113		T16	1
valid_sources[0x04]	21871	1		T5	61		T8	535		T10	1
valid_sources[0x05]	24107	1		T5	1001		T8	899		T9	26
valid_sources[0x06]	24309	1		T5	40		T6	6		T8	1441
valid_sources[0x07]	24995	1		T5	276		T8	884		T13	1
valid_sources[0x08]	25199	1		T5	578		T8	1069		T13	1
valid_sources[0x09]	24024	1		T5	233		T8	1210		T10	1
valid_sources[0x0a]	24954	1		T5	330		T8	565		T9	31
valid_sources[0x0b]	24868	1		T5	238		T8	1305		T15	3
valid_sources[0x0c]	23393	1		T4	1		T5	205		T8	1100
valid_sources[0x0d]	23189	1		T5	196		T8	914		T10	1
valid_sources[0x0e]	25081	1		T5	205		T8	1182		T10	2
valid_sources[0x0f]	24515	1		T5	179		T8	1238		T10	5
valid_sources[0x10]	22100	1		T5	296		T8	409		T9	8
valid_sources[0x11]	23508	1		T5	490		T8	1190		T10	2
valid_sources[0x12]	22206	1		T5	269		T8	460		T16	3
valid_sources[0x13]	24022	1		T5	141		T8	1271		T10	1
valid_sources[0x14]	23458	1		T5	506		T8	594		T9	9
valid_sources[0x15]	23756	1		T5	195		T8	971		T15	5
valid_sources[0x16]	24475	1		T5	308		T8	1584		T16	1
valid_sources[0x17]	23515	1		T5	38		T8	642		T10	2
valid_sources[0x18]	23371	1		T5	737		T8	1180		T16	1
valid_sources[0x19]	23679	1		T5	55		T7	3		T8	856
valid_sources[0x1a]	24482	1		T5	209		T6	6		T8	1024
valid_sources[0x1b]	25158	1		T1	13		T5	261		T8	1374
valid_sources[0x1c]	25214	1		T5	74		T8	1175		T12	1
valid_sources[0x1d]	24879	1		T5	297		T8	1231		T10	2
valid_sources[0x1e]	25504	1		T5	136		T7	1		T8	1231
valid_sources[0x1f]	23278	1		T5	56		T8	955		T10	2
valid_sources[0x20]	26026	1		T2	1		T5	876		T8	1020
valid_sources[0x21]	22658	1		T5	82		T8	838		T17	657
valid_sources[0x22]	23089	1		T5	725		T8	588		T10	5
valid_sources[0x23]	23168	1		T3	1		T5	383		T8	1135
valid_sources[0x24]	22063	1		T5	222		T8	800		T13	1
valid_sources[0x25]	24171	1		T5	370		T8	1339		T10	2
valid_sources[0x26]	22697	1		T5	365		T8	1230		T16	1
valid_sources[0x27]	23267	1		T5	489		T8	871		T15	1
valid_sources[0x28]	25143	1		T5	200		T8	1724		T17	696
valid_sources[0x29]	25505	1		T5	200		T8	1565		T14	1
valid_sources[0x2a]	23248	1		T5	392		T8	932		T22	1
valid_sources[0x2b]	23523	1		T3	2		T5	107		T8	1259
valid_sources[0x2c]	24635	1		T5	53		T8	442		T16	1
valid_sources[0x2d]	25119	1		T5	212		T8	553		T14	1
valid_sources[0x2e]	25124	1		T5	864		T8	1638		T14	2
valid_sources[0x2f]	23256	1		T5	101		T7	3		T8	749
valid_sources[0x30]	24215	1		T5	493		T8	931		T10	1
valid_sources[0x31]	23333	1		T5	1096		T8	354		T9	11
valid_sources[0x32]	24328	1		T5	366		T8	886		T10	5
valid_sources[0x33]	24853	1		T5	450		T8	940		T10	1
valid_sources[0x34]	23180	1		T5	190		T8	859		T10	1
valid_sources[0x35]	23649	1		T5	248		T8	956		T17	608
valid_sources[0x36]	23561	1		T2	1		T5	116		T8	1315
valid_sources[0x37]	24136	1		T2	1		T5	628		T8	232
valid_sources[0x38]	24913	1		T5	293		T8	1135		T17	657
valid_sources[0x39]	23253	1		T5	460		T8	1320		T10	1
valid_sources[0x3a]	23511	1		T5	317		T8	604		T15	3
valid_sources[0x3b]	24185	1		T5	344		T6	3		T8	1209
valid_sources[0x3c]	25016	1		T5	753		T8	624		T10	1
valid_sources[0x3d]	23128	1		T5	463		T8	942		T16	1
valid_sources[0x3e]	25194	1		T5	108		T8	913		T10	4
valid_sources[0x3f]	24665	1		T5	586		T8	1344		T16	1
valid_sources[0x40]	26234	1		T2	1		T5	783		T8	609
valid_sources[0x41]	23392	1		T5	216		T8	1532		T15	2
valid_sources[0x42]	24343	1		T5	375		T8	1226		T10	4
valid_sources[0x43]	25057	1		T5	492		T8	857		T10	1
valid_sources[0x44]	22725	1		T5	335		T8	1072		T16	1
valid_sources[0x45]	25630	1		T5	410		T8	1530		T10	3
valid_sources[0x46]	25996	1		T1	19		T4	1		T5	391
valid_sources[0x47]	23359	1		T5	141		T8	990		T9	11
valid_sources[0x48]	25093	1		T5	522		T8	1381		T15	11
valid_sources[0x49]	24920	1		T5	617		T8	843		T10	2
valid_sources[0x4a]	24557	1		T5	485		T8	1147		T16	1
valid_sources[0x4b]	22970	1		T5	111		T8	1215		T9	5
valid_sources[0x4c]	25353	1		T2	2		T5	615		T8	835
valid_sources[0x4d]	25122	1		T5	193		T8	1289		T16	2
valid_sources[0x4e]	24936	1		T4	1		T5	228		T8	677
valid_sources[0x4f]	25386	1		T5	913		T8	1624		T16	1
valid_sources[0x50]	24465	1		T5	265		T8	1067		T10	3
valid_sources[0x51]	23565	1		T3	2		T5	356		T8	1122
valid_sources[0x52]	24369	1		T5	138		T8	1245		T10	1
valid_sources[0x53]	25769	1		T5	198		T8	1109		T16	2
valid_sources[0x54]	27107	1		T5	136		T8	1903		T10	8
valid_sources[0x55]	25634	1		T5	675		T8	1438		T16	5
valid_sources[0x56]	25403	1		T5	430		T8	1828		T22	1
valid_sources[0x57]	23927	1		T5	234		T8	1035		T10	1
valid_sources[0x58]	25103	1		T5	492		T8	1274		T10	1
valid_sources[0x59]	25580	1		T5	628		T8	1214		T17	706
valid_sources[0x5a]	23576	1		T5	461		T8	1059		T10	1
valid_sources[0x5b]	26303	1		T5	480		T6	1		T8	1698
valid_sources[0x5c]	22367	1		T5	231		T7	1		T8	986
valid_sources[0x5d]	24794	1		T4	1		T5	171		T8	865
valid_sources[0x5e]	24732	1		T5	660		T8	887		T10	1
valid_sources[0x5f]	22406	1		T5	511		T8	848		T16	1
valid_sources[0x60]	25167	1		T5	340		T8	613		T17	640
valid_sources[0x61]	23957	1		T5	155		T8	668		T10	1
valid_sources[0x62]	23340	1		T5	196		T8	1109		T9	4
valid_sources[0x63]	24621	1		T5	206		T8	960		T10	3
valid_sources[0x64]	24431	1		T5	144		T8	854		T10	1
valid_sources[0x65]	25424	1		T5	262		T8	1139		T16	2
valid_sources[0x66]	25006	1		T5	348		T8	935		T13	1
valid_sources[0x67]	23204	1		T3	1		T5	140		T7	1
valid_sources[0x68]	23003	1		T5	326		T8	861		T16	1
valid_sources[0x69]	24039	1		T5	639		T8	1018		T16	3
valid_sources[0x6a]	23119	1		T5	553		T8	1033		T10	1
valid_sources[0x6b]	23933	1		T5	274		T6	1		T7	4
valid_sources[0x6c]	22811	1		T5	384		T8	900		T10	1
valid_sources[0x6d]	25440	1		T5	441		T8	978		T16	2
valid_sources[0x6e]	24374	1		T5	862		T8	448		T15	6
valid_sources[0x6f]	26653	1		T3	1		T5	325		T8	1000
valid_sources[0x70]	24418	1		T5	674		T8	528		T10	3
valid_sources[0x71]	23639	1		T5	176		T8	964		T10	1
valid_sources[0x72]	23986	1		T3	1		T5	380		T8	1449
valid_sources[0x73]	24619	1		T5	128		T8	1115		T15	1
valid_sources[0x74]	27422	1		T5	364		T8	977		T15	9
valid_sources[0x75]	21876	1		T5	319		T8	887		T10	3
valid_sources[0x76]	24526	1		T5	400		T8	987		T12	1
valid_sources[0x77]	25051	1		T5	230		T8	723		T10	1
valid_sources[0x78]	22463	1		T5	129		T8	655		T16	1
valid_sources[0x79]	23422	1		T4	1		T5	322		T8	1010
valid_sources[0x7a]	26011	1		T5	105		T8	1061		T10	2
valid_sources[0x7b]	23928	1		T5	499		T8	1684		T16	2
valid_sources[0x7c]	24504	1		T2	1		T5	165		T8	1248
valid_sources[0x7d]	24839	1		T5	197		T8	1361		T10	3
valid_sources[0x7e]	25046	1		T2	1		T4	1		T5	375
valid_sources[0x7f]	25878	1		T5	431		T8	1494		T16	1
valid_sources[0x80]	23918	1		T5	681		T8	936		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1450066

1

T1

23

T2

2

T3

1

values[0x0]

all_enables

biggest_size

2169883

1

T1

69

T2

7

T3

4

values[0x1]

all_enables

biggest_size

2173457

1

T1

56

T2

3

T3

4