Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	770080631	8282897	0	0
wdog_bark_thold_rd_A	770080631	149034	0	0
wdog_bite_thold_rd_A	770080631	130522	0	0
wdog_ctrl_rd_A	770080631	129946	0	0
wdog_regwen_rd_A	770080631	149699	0	0
wkup_ctrl_rd_A	770080631	130575	0	0
wkup_thold_rd_A	770080631	147376	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770080631	8282897	0	0
T5	448968	114377	0	0
T6	19413	0	0	0
T7	13184	0	0	0
T8	772887	354817	0	0
T9	218070	0	0	0
T10	200737	0	0	0
T11	741408	0	0	0
T12	136873	0	0	0
T13	50184	0	0	0
T14	22402	0	0	0
T17	0	215914	0	0
T26	0	119501	0	0
T28	0	71040	0	0
T29	0	80379	0	0
T30	0	228507	0	0
T31	0	75936	0	0
T32	0	184215	0	0
T33	0	117340	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770080631	149034	0	0
T5	448968	9716	0	0
T6	19413	0	0	0
T7	13184	0	0	0
T8	772887	0	0	0
T9	218070	0	0	0
T10	200737	0	0	0
T11	741408	0	0	0
T12	136873	0	0	0
T13	50184	0	0	0
T14	22402	0	0	0
T17	0	18370	0	0
T28	0	5720	0	0
T31	0	6260	0	0
T33	0	10171	0	0
T78	0	5183	0	0
T79	0	26286	0	0
T80	0	4508	0	0
T81	0	7750	0	0
T82	0	6963	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770080631	130522	0	0
T5	448968	8446	0	0
T6	19413	0	0	0
T7	13184	0	0	0
T8	772887	0	0	0
T9	218070	0	0	0
T10	200737	0	0	0
T11	741408	0	0	0
T12	136873	0	0	0
T13	50184	0	0	0
T14	22402	0	0	0
T17	0	16689	0	0
T28	0	5087	0	0
T31	0	5654	0	0
T33	0	8952	0	0
T78	0	4512	0	0
T79	0	22618	0	0
T80	0	4182	0	0
T81	0	6980	0	0
T82	0	5731	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770080631	129946	0	0
T5	448968	8260	0	0
T6	19413	0	0	0
T7	13184	0	0	0
T8	772887	0	0	0
T9	218070	0	0	0
T10	200737	0	0	0
T11	741408	0	0	0
T12	136873	0	0	0
T13	50184	0	0	0
T14	22402	0	0	0
T17	0	15964	0	0
T28	0	5065	0	0
T31	0	5161	0	0
T33	0	9200	0	0
T78	0	4726	0	0
T79	0	22515	0	0
T80	0	4221	0	0
T81	0	7035	0	0
T82	0	6084	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770080631	149699	0	0
T5	448968	9489	0	0
T6	19413	0	0	0
T7	13184	0	0	0
T8	772887	0	0	0
T9	218070	0	0	0
T10	200737	0	0	0
T11	741408	0	0	0
T12	136873	0	0	0
T13	50184	0	0	0
T14	22402	0	0	0
T17	0	18685	0	0
T28	0	6079	0	0
T31	0	6123	0	0
T33	0	10308	0	0
T78	0	5168	0	0
T79	0	26659	0	0
T80	0	4722	0	0
T81	0	7940	0	0
T82	0	6888	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770080631	130575	0	0
T5	448968	8164	0	0
T6	19413	0	0	0
T7	13184	0	0	0
T8	772887	0	0	0
T9	218070	0	0	0
T10	200737	0	0	0
T11	741408	0	0	0
T12	136873	0	0	0
T13	50184	0	0	0
T14	22402	0	0	0
T17	0	15909	0	0
T28	0	5155	0	0
T31	0	5833	0	0
T33	0	8822	0	0
T78	0	4766	0	0
T79	0	23280	0	0
T80	0	3873	0	0
T81	0	6993	0	0
T82	0	6010	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770080631	147376	0	0
T5	448968	9267	0	0
T6	19413	0	0	0
T7	13184	0	0	0
T8	772887	0	0	0
T9	218070	0	0	0
T10	200737	0	0	0
T11	741408	0	0	0
T12	136873	0	0	0
T13	50184	0	0	0
T14	22402	0	0	0
T17	0	18139	0	0
T28	0	5655	0	0
T31	0	6306	0	0
T33	0	10086	0	0
T78	0	5068	0	0
T79	0	26137	0	0
T80	0	4859	0	0
T81	0	8012	0	0
T82	0	6713	0	0