Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	338443	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4119356	1		T1	231		T2	60249		T3	237

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1095020	1		T1	21		T2	16021		T3	47
values[0x0]	1575276	1		T1	149		T2	22973		T3	140
values[0x1]	1787503	1		T1	152		T2	26330		T3	152

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151535	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4306264	1		T1	248		T2	63149		T3	263

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16408	1		T2	284		T3	1		T14	238
valid_sources[0x01]	17610	1		T2	252		T3	3		T14	233
valid_sources[0x02]	17693	1		T2	235		T3	2		T14	259
valid_sources[0x03]	17725	1		T2	217		T6	1		T14	285
valid_sources[0x04]	18660	1		T2	187		T3	2		T14	222
valid_sources[0x05]	16701	1		T1	1		T2	213		T6	1
valid_sources[0x06]	17225	1		T1	1		T2	271		T3	2
valid_sources[0x07]	16995	1		T2	295		T5	5		T14	259
valid_sources[0x08]	18976	1		T2	257		T3	1		T6	2
valid_sources[0x09]	18214	1		T1	5		T2	232		T12	1
valid_sources[0x0a]	17289	1		T1	5		T2	261		T3	3
valid_sources[0x0b]	16906	1		T1	2		T2	259		T6	3
valid_sources[0x0c]	16687	1		T1	1		T2	278		T3	1
valid_sources[0x0d]	17017	1		T2	193		T3	2		T14	244
valid_sources[0x0e]	17662	1		T1	10		T2	254		T6	1
valid_sources[0x0f]	15738	1		T1	10		T2	216		T3	3
valid_sources[0x10]	17839	1		T2	300		T3	1		T6	1
valid_sources[0x11]	16483	1		T2	266		T3	3		T6	6
valid_sources[0x12]	17653	1		T2	259		T3	1		T6	1
valid_sources[0x13]	18931	1		T1	7		T2	289		T3	2
valid_sources[0x14]	17789	1		T2	254		T3	3		T14	270
valid_sources[0x15]	17211	1		T1	2		T2	272		T6	4
valid_sources[0x16]	18710	1		T2	256		T6	1		T14	229
valid_sources[0x17]	17317	1		T1	1		T2	253		T14	250
valid_sources[0x18]	18202	1		T2	265		T3	2		T6	2
valid_sources[0x19]	17576	1		T2	252		T3	1		T14	217
valid_sources[0x1a]	16647	1		T2	227		T3	2		T6	1
valid_sources[0x1b]	17432	1		T1	2		T2	211		T3	2
valid_sources[0x1c]	17520	1		T2	239		T14	230		T15	1
valid_sources[0x1d]	16642	1		T2	230		T6	1		T14	271
valid_sources[0x1e]	17407	1		T1	11		T2	271		T3	1
valid_sources[0x1f]	17186	1		T2	245		T3	2		T7	20
valid_sources[0x20]	17018	1		T2	341		T6	2		T14	247
valid_sources[0x21]	17764	1		T2	250		T6	3		T14	254
valid_sources[0x22]	16150	1		T1	2		T2	288		T6	3
valid_sources[0x23]	17698	1		T2	229		T3	3		T4	22
valid_sources[0x24]	17399	1		T2	236		T3	3		T6	1
valid_sources[0x25]	17408	1		T2	202		T3	3		T6	1
valid_sources[0x26]	17691	1		T1	4		T2	289		T3	1
valid_sources[0x27]	16797	1		T2	224		T3	1		T6	2
valid_sources[0x28]	17692	1		T2	240		T6	3		T14	234
valid_sources[0x29]	17001	1		T2	211		T14	271		T18	252
valid_sources[0x2a]	17672	1		T2	264		T3	1		T6	3
valid_sources[0x2b]	17358	1		T2	228		T14	225		T15	1
valid_sources[0x2c]	18204	1		T2	257		T3	3		T6	1
valid_sources[0x2d]	18535	1		T2	246		T14	257		T37	2
valid_sources[0x2e]	17952	1		T1	1		T2	356		T14	222
valid_sources[0x2f]	17477	1		T2	197		T5	2		T14	260
valid_sources[0x30]	18230	1		T2	200		T5	1		T6	3
valid_sources[0x31]	17727	1		T1	1		T2	263		T3	3
valid_sources[0x32]	17408	1		T1	3		T2	306		T3	1
valid_sources[0x33]	16964	1		T2	222		T3	2		T14	236
valid_sources[0x34]	15240	1		T2	220		T14	234		T15	3
valid_sources[0x35]	17941	1		T2	235		T3	2		T6	1
valid_sources[0x36]	17335	1		T2	270		T3	1		T14	277
valid_sources[0x37]	17326	1		T2	271		T3	1		T12	2
valid_sources[0x38]	16569	1		T1	8		T2	242		T3	2
valid_sources[0x39]	18275	1		T2	223		T3	1		T8	1
valid_sources[0x3a]	16841	1		T2	257		T6	1		T14	250
valid_sources[0x3b]	17474	1		T1	3		T2	213		T3	2
valid_sources[0x3c]	18365	1		T1	8		T2	248		T3	3
valid_sources[0x3d]	16550	1		T2	233		T3	2		T6	1
valid_sources[0x3e]	18171	1		T2	260		T3	1		T6	4
valid_sources[0x3f]	18028	1		T2	269		T3	2		T14	285
valid_sources[0x40]	17315	1		T2	282		T3	1		T14	251
valid_sources[0x41]	17100	1		T2	258		T3	1		T6	3
valid_sources[0x42]	17111	1		T2	271		T8	1		T14	251
valid_sources[0x43]	17655	1		T2	300		T3	3		T14	262
valid_sources[0x44]	18419	1		T2	191		T3	1		T14	253
valid_sources[0x45]	18896	1		T1	9		T2	205		T3	3
valid_sources[0x46]	16414	1		T2	252		T14	209		T15	3
valid_sources[0x47]	17804	1		T2	222		T3	1		T8	1
valid_sources[0x48]	18452	1		T2	331		T3	2		T6	1
valid_sources[0x49]	17001	1		T2	232		T3	3		T6	2
valid_sources[0x4a]	17497	1		T2	227		T3	2		T14	234
valid_sources[0x4b]	16936	1		T2	284		T6	1		T14	243
valid_sources[0x4c]	17105	1		T1	3		T2	298		T3	1
valid_sources[0x4d]	18067	1		T2	226		T6	2		T14	242
valid_sources[0x4e]	16193	1		T2	257		T6	3		T14	266
valid_sources[0x4f]	17092	1		T2	258		T6	5		T12	1
valid_sources[0x50]	16728	1		T2	220		T3	1		T6	2
valid_sources[0x51]	17517	1		T2	218		T3	2		T14	258
valid_sources[0x52]	17499	1		T1	15		T2	328		T6	1
valid_sources[0x53]	18006	1		T1	5		T2	301		T3	1
valid_sources[0x54]	16815	1		T2	256		T6	1		T14	222
valid_sources[0x55]	15592	1		T2	188		T3	3		T12	2
valid_sources[0x56]	17158	1		T1	1		T2	259		T3	1
valid_sources[0x57]	17553	1		T1	9		T2	253		T3	1
valid_sources[0x58]	18067	1		T2	227		T6	1		T14	253
valid_sources[0x59]	16740	1		T2	302		T3	2		T6	2
valid_sources[0x5a]	16919	1		T1	3		T2	287		T14	219
valid_sources[0x5b]	17314	1		T2	244		T3	1		T6	1
valid_sources[0x5c]	16862	1		T2	260		T3	1		T14	261
valid_sources[0x5d]	17311	1		T2	263		T3	1		T6	3
valid_sources[0x5e]	16794	1		T2	267		T6	1		T14	245
valid_sources[0x5f]	18008	1		T2	261		T3	2		T6	4
valid_sources[0x60]	17025	1		T2	293		T3	1		T14	258
valid_sources[0x61]	17122	1		T2	259		T3	2		T6	1
valid_sources[0x62]	17371	1		T2	267		T3	1		T8	1
valid_sources[0x63]	16867	1		T1	14		T2	269		T14	249
valid_sources[0x64]	16190	1		T2	256		T3	2		T6	1
valid_sources[0x65]	16772	1		T1	5		T2	241		T3	1
valid_sources[0x66]	17303	1		T2	282		T3	3		T6	2
valid_sources[0x67]	18402	1		T1	2		T2	231		T3	2
valid_sources[0x68]	17807	1		T1	4		T2	255		T6	1
valid_sources[0x69]	16946	1		T2	262		T3	2		T6	1
valid_sources[0x6a]	16539	1		T2	267		T6	2		T14	275
valid_sources[0x6b]	17776	1		T1	7		T2	269		T6	2
valid_sources[0x6c]	17546	1		T2	237		T3	3		T14	267
valid_sources[0x6d]	17565	1		T2	288		T3	1		T6	1
valid_sources[0x6e]	18592	1		T2	276		T14	246		T15	1
valid_sources[0x6f]	16906	1		T2	338		T3	2		T6	2
valid_sources[0x70]	18378	1		T2	236		T3	1		T6	3
valid_sources[0x71]	16923	1		T1	2		T2	230		T3	1
valid_sources[0x72]	17525	1		T2	316		T3	1		T14	227
valid_sources[0x73]	17536	1		T2	291		T10	1		T14	243
valid_sources[0x74]	17032	1		T2	217		T3	1		T6	2
valid_sources[0x75]	17145	1		T2	282		T3	2		T14	240
valid_sources[0x76]	17319	1		T2	232		T3	1		T6	2
valid_sources[0x77]	16566	1		T2	198		T3	2		T6	3
valid_sources[0x78]	17211	1		T2	213		T3	2		T6	1
valid_sources[0x79]	17771	1		T1	1		T2	276		T3	1
valid_sources[0x7a]	17037	1		T2	295		T3	1		T14	268
valid_sources[0x7b]	17008	1		T2	262		T3	1		T14	257
valid_sources[0x7c]	17286	1		T1	2		T2	297		T3	2
valid_sources[0x7d]	17552	1		T1	1		T2	265		T3	2
valid_sources[0x7e]	17626	1		T2	230		T3	1		T6	3
valid_sources[0x7f]	17061	1		T2	263		T3	3		T6	1
valid_sources[0x80]	16983	1		T2	276		T3	1		T14	261

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1026480

1

T1

8

T2

15037

T3

24

values[0x0]

all_enables

biggest_size

1546357

1

T1

115

T2

22596

T3

105

values[0x1]

all_enables

biggest_size

1546519

1

T1

108

T2

22616

T3

108