Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	659786821	4881817	0	0
wdog_bark_thold_rd_A	659786821	120906	0	0
wdog_bite_thold_rd_A	659786821	104397	0	0
wdog_ctrl_rd_A	659786821	103583	0	0
wdog_regwen_rd_A	659786821	120200	0	0
wkup_ctrl_rd_A	659786821	104610	0	0
wkup_thold_hi_rd_A	659786821	120587	0	0
wkup_thold_lo_rd_A	659786821	104844	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659786821	4881817	0	0
T2	198477	76090	0	0
T3	278287	0	0	0
T4	12052	0	0	0
T5	370042	0	0	0
T6	716542	0	0	0
T7	209434	0	0	0
T8	9778	0	0	0
T9	42440	0	0	0
T10	39802	0	0	0
T11	780673	0	0	0
T14	0	68756	0	0
T18	0	66758	0	0
T27	0	54638	0	0
T31	0	46393	0	0
T32	0	51076	0	0
T33	0	78563	0	0
T34	0	72540	0	0
T35	0	32651	0	0
T36	0	135151	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659786821	120906	0	0
T18	599597	6250	0	0
T27	160866	0	0	0
T31	129939	0	0	0
T32	216316	3008	0	0
T33	0	7864	0	0
T34	0	7438	0	0
T38	235059	0	0	0
T39	137059	0	0	0
T40	5719	0	0	0
T42	794577	0	0	0
T43	40206	0	0	0
T44	28046	0	0	0
T65	0	11736	0	0
T67	0	9747	0	0
T72	0	27604	0	0
T73	0	3891	0	0
T74	0	12964	0	0
T75	0	7144	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659786821	104397	0	0
T18	599597	5325	0	0
T27	160866	0	0	0
T31	129939	0	0	0
T32	216316	2535	0	0
T33	0	6830	0	0
T34	0	6441	0	0
T38	235059	0	0	0
T39	137059	0	0	0
T40	5719	0	0	0
T42	794577	0	0	0
T43	40206	0	0	0
T44	28046	0	0	0
T65	0	9821	0	0
T67	0	8442	0	0
T72	0	23510	0	0
T73	0	3444	0	0
T74	0	11227	0	0
T75	0	6428	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659786821	103583	0	0
T18	599597	5680	0	0
T27	160866	0	0	0
T31	129939	0	0	0
T32	216316	2466	0	0
T33	0	6607	0	0
T34	0	6448	0	0
T38	235059	0	0	0
T39	137059	0	0	0
T40	5719	0	0	0
T42	794577	0	0	0
T43	40206	0	0	0
T44	28046	0	0	0
T65	0	9528	0	0
T67	0	8422	0	0
T72	0	23345	0	0
T73	0	3305	0	0
T74	0	10906	0	0
T75	0	6089	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659786821	120200	0	0
T18	599597	6562	0	0
T27	160866	0	0	0
T31	129939	0	0	0
T32	216316	2642	0	0
T33	0	8188	0	0
T34	0	7263	0	0
T38	235059	0	0	0
T39	137059	0	0	0
T40	5719	0	0	0
T42	794577	0	0	0
T43	40206	0	0	0
T44	28046	0	0	0
T65	0	12124	0	0
T67	0	9679	0	0
T72	0	27140	0	0
T73	0	3347	0	0
T74	0	12481	0	0
T75	0	7226	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659786821	104610	0	0
T18	599597	5600	0	0
T27	160866	0	0	0
T31	129939	0	0	0
T32	216316	2240	0	0
T33	0	6842	0	0
T34	0	6362	0	0
T38	235059	0	0	0
T39	137059	0	0	0
T40	5719	0	0	0
T42	794577	0	0	0
T43	40206	0	0	0
T44	28046	0	0	0
T65	0	10187	0	0
T67	0	8743	0	0
T72	0	23335	0	0
T73	0	3462	0	0
T74	0	11178	0	0
T75	0	6014	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659786821	120587	0	0
T18	599597	6660	0	0
T27	160866	0	0	0
T31	129939	0	0	0
T32	216316	3042	0	0
T33	0	7821	0	0
T34	0	7634	0	0
T38	235059	0	0	0
T39	137059	0	0	0
T40	5719	0	0	0
T42	794577	0	0	0
T43	40206	0	0	0
T44	28046	0	0	0
T65	0	11170	0	0
T67	0	10034	0	0
T72	0	27403	0	0
T73	0	3771	0	0
T74	0	12265	0	0
T75	0	7162	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659786821	104844	0	0
T18	599597	5250	0	0
T27	160866	0	0	0
T31	129939	0	0	0
T32	216316	2447	0	0
T33	0	7211	0	0
T34	0	6536	0	0
T38	235059	0	0	0
T39	137059	0	0	0
T40	5719	0	0	0
T42	794577	0	0	0
T43	40206	0	0	0
T44	28046	0	0	0
T65	0	9022	0	0
T67	0	8596	0	0
T72	0	24807	0	0
T73	0	2826	0	0
T74	0	10977	0	0
T75	0	6304	0	0