Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	672405159	5596474	0	0
wdog_bark_thold_rd_A	672405159	138162	0	0
wdog_bite_thold_rd_A	672405159	123269	0	0
wdog_ctrl_rd_A	672405159	123180	0	0
wdog_regwen_rd_A	672405159	141213	0	0
wkup_ctrl_rd_A	672405159	123695	0	0
wkup_thold_hi_rd_A	672405159	140594	0	0
wkup_thold_lo_rd_A	672405159	122372	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672405159	5596474	0	0
T7	914193	128315	0	0
T8	633452	0	0	0
T9	462158	0	0	0
T10	179968	0	0	0
T11	479353	127732	0	0
T12	179282	60422	0	0
T19	0	152441	0	0
T27	14225	0	0	0
T28	110172	178337	0	0
T29	129506	0	0	0
T35	676044	241916	0	0
T36	0	234880	0	0
T37	0	201197	0	0
T38	0	296261	0	0
T39	0	185259	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672405159	138162	0	0
T7	914193	6897	0	0
T8	633452	0	0	0
T9	462158	0	0	0
T10	179968	0	0	0
T11	479353	0	0	0
T12	179282	0	0	0
T27	14225	0	0	0
T28	110172	17355	0	0
T29	129506	0	0	0
T35	676044	0	0	0
T38	0	15745	0	0
T46	0	5660	0	0
T82	0	5341	0	0
T83	0	2610	0	0
T84	0	7062	0	0
T85	0	14802	0	0
T86	0	17068	0	0
T87	0	12661	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672405159	123269	0	0
T7	914193	6084	0	0
T8	633452	0	0	0
T9	462158	0	0	0
T10	179968	0	0	0
T11	479353	0	0	0
T12	179282	0	0	0
T27	14225	0	0	0
T28	110172	15174	0	0
T29	129506	0	0	0
T35	676044	0	0	0
T38	0	13610	0	0
T46	0	5473	0	0
T82	0	4739	0	0
T83	0	2571	0	0
T84	0	6480	0	0
T85	0	14067	0	0
T86	0	15543	0	0
T87	0	11044	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672405159	123180	0	0
T7	914193	5993	0	0
T8	633452	0	0	0
T9	462158	0	0	0
T10	179968	0	0	0
T11	479353	0	0	0
T12	179282	0	0	0
T27	14225	0	0	0
T28	110172	15347	0	0
T29	129506	0	0	0
T35	676044	0	0	0
T38	0	14058	0	0
T46	0	5092	0	0
T82	0	5183	0	0
T83	0	2302	0	0
T84	0	5893	0	0
T85	0	13955	0	0
T86	0	15315	0	0
T87	0	10588	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672405159	141213	0	0
T7	914193	6791	0	0
T8	633452	0	0	0
T9	462158	0	0	0
T10	179968	0	0	0
T11	479353	0	0	0
T12	179282	0	0	0
T27	14225	0	0	0
T28	110172	17477	0	0
T29	129506	0	0	0
T35	676044	0	0	0
T38	0	15529	0	0
T46	0	5914	0	0
T82	0	5883	0	0
T83	0	2852	0	0
T84	0	6879	0	0
T85	0	15763	0	0
T86	0	17503	0	0
T87	0	13377	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672405159	123695	0	0
T7	914193	6029	0	0
T8	633452	0	0	0
T9	462158	0	0	0
T10	179968	0	0	0
T11	479353	0	0	0
T12	179282	0	0	0
T27	14225	0	0	0
T28	110172	15478	0	0
T29	129506	0	0	0
T35	676044	0	0	0
T38	0	13978	0	0
T46	0	5336	0	0
T82	0	5174	0	0
T83	0	2485	0	0
T84	0	5928	0	0
T85	0	14105	0	0
T86	0	15571	0	0
T87	0	11131	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672405159	140594	0	0
T7	914193	6932	0	0
T8	633452	0	0	0
T9	462158	0	0	0
T10	179968	0	0	0
T11	479353	0	0	0
T12	179282	0	0	0
T27	14225	0	0	0
T28	110172	16890	0	0
T29	129506	0	0	0
T35	676044	0	0	0
T38	0	16184	0	0
T46	0	5907	0	0
T82	0	6005	0	0
T83	0	2729	0	0
T84	0	7509	0	0
T85	0	15276	0	0
T86	0	18024	0	0
T87	0	12646	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672405159	122372	0	0
T7	914193	6097	0	0
T8	633452	0	0	0
T9	462158	0	0	0
T10	179968	0	0	0
T11	479353	0	0	0
T12	179282	0	0	0
T27	14225	0	0	0
T28	110172	15205	0	0
T29	129506	0	0	0
T35	676044	0	0	0
T38	0	13550	0	0
T46	0	5200	0	0
T82	0	5222	0	0
T83	0	2225	0	0
T84	0	6273	0	0
T85	0	13834	0	0
T86	0	15240	0	0
T87	0	10954	0	0