Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	379572	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4648969	1		T1	221		T2	13		T3	12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1234945	1		T1	26		T2	1		T3	1
values[0x0]	1776578	1		T1	146		T2	8		T3	11
values[0x1]	2017018	1		T1	134		T2	11		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	168745	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4859796	1		T1	236		T2	13		T3	13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19155	1		T6	382		T8	291		T10	3
valid_sources[0x01]	19671	1		T2	1		T6	332		T8	273
valid_sources[0x02]	19347	1		T5	1		T6	288		T8	291
valid_sources[0x03]	19575	1		T5	1		T6	395		T8	366
valid_sources[0x04]	19536	1		T5	4		T6	343		T8	244
valid_sources[0x05]	19616	1		T5	1		T6	335		T8	340
valid_sources[0x06]	20147	1		T3	5		T6	357		T8	259
valid_sources[0x07]	20195	1		T5	1		T6	367		T8	320
valid_sources[0x08]	19188	1		T3	3		T6	343		T8	294
valid_sources[0x09]	20079	1		T2	1		T5	1		T6	312
valid_sources[0x0a]	19729	1		T6	343		T8	272		T11	1
valid_sources[0x0b]	18149	1		T5	2		T6	390		T8	269
valid_sources[0x0c]	18230	1		T5	2		T6	312		T8	277
valid_sources[0x0d]	20584	1		T5	2		T6	397		T8	299
valid_sources[0x0e]	21209	1		T5	2		T6	329		T8	246
valid_sources[0x0f]	19428	1		T5	4		T6	285		T8	333
valid_sources[0x10]	19731	1		T5	4		T6	344		T8	281
valid_sources[0x11]	19377	1		T5	2		T6	311		T8	247
valid_sources[0x12]	18925	1		T2	1		T5	2		T6	344
valid_sources[0x13]	18879	1		T3	2		T5	3		T6	318
valid_sources[0x14]	20155	1		T5	1		T6	415		T7	1
valid_sources[0x15]	20099	1		T5	1		T6	364		T8	339
valid_sources[0x16]	20111	1		T5	2		T6	335		T8	280
valid_sources[0x17]	20437	1		T6	391		T8	309		T11	1
valid_sources[0x18]	19308	1		T6	359		T8	282		T12	206
valid_sources[0x19]	20838	1		T5	1		T6	338		T8	284
valid_sources[0x1a]	18138	1		T5	2		T6	338		T8	254
valid_sources[0x1b]	20040	1		T6	359		T8	250		T9	1
valid_sources[0x1c]	19618	1		T5	3		T6	289		T8	274
valid_sources[0x1d]	20677	1		T5	1		T6	390		T8	276
valid_sources[0x1e]	19140	1		T6	322		T8	299		T11	1
valid_sources[0x1f]	17896	1		T5	1		T6	356		T8	279
valid_sources[0x20]	20021	1		T5	3		T6	309		T8	267
valid_sources[0x21]	19644	1		T5	1		T6	275		T8	271
valid_sources[0x22]	19795	1		T6	311		T8	326		T11	1
valid_sources[0x23]	19477	1		T5	2		T6	256		T8	294
valid_sources[0x24]	18870	1		T6	369		T8	292		T11	1
valid_sources[0x25]	18985	1		T3	1		T5	1		T6	324
valid_sources[0x26]	19620	1		T6	330		T8	276		T9	1
valid_sources[0x27]	20370	1		T6	325		T8	272		T11	1
valid_sources[0x28]	17938	1		T5	4		T6	310		T8	275
valid_sources[0x29]	20249	1		T5	1		T6	316		T8	265
valid_sources[0x2a]	20312	1		T2	3		T6	324		T8	238
valid_sources[0x2b]	21449	1		T5	1		T6	364		T8	310
valid_sources[0x2c]	19662	1		T5	2		T6	361		T8	243
valid_sources[0x2d]	19363	1		T6	359		T7	1		T8	317
valid_sources[0x2e]	19154	1		T5	2		T6	321		T8	285
valid_sources[0x2f]	21829	1		T2	5		T6	295		T8	299
valid_sources[0x30]	19282	1		T5	1		T6	322		T8	268
valid_sources[0x31]	20429	1		T5	1		T6	341		T8	291
valid_sources[0x32]	20210	1		T6	330		T8	304		T12	196
valid_sources[0x33]	19816	1		T5	3		T6	356		T8	308
valid_sources[0x34]	18751	1		T5	2		T6	343		T8	267
valid_sources[0x35]	19210	1		T5	2		T6	363		T8	293
valid_sources[0x36]	19202	1		T5	1		T6	339		T8	293
valid_sources[0x37]	19543	1		T6	398		T7	2		T8	301
valid_sources[0x38]	19884	1		T6	338		T8	281		T12	215
valid_sources[0x39]	20076	1		T6	375		T8	293		T11	2
valid_sources[0x3a]	21703	1		T6	309		T8	339		T11	1
valid_sources[0x3b]	20656	1		T6	373		T8	309		T11	3
valid_sources[0x3c]	20010	1		T5	2		T6	359		T8	296
valid_sources[0x3d]	19735	1		T5	5		T6	386		T8	263
valid_sources[0x3e]	19841	1		T1	306		T6	287		T8	347
valid_sources[0x3f]	20184	1		T2	1		T6	405		T8	286
valid_sources[0x40]	19702	1		T5	2		T6	341		T8	267
valid_sources[0x41]	19690	1		T5	1		T6	357		T8	275
valid_sources[0x42]	19826	1		T6	412		T8	275		T12	205
valid_sources[0x43]	20782	1		T5	1		T6	304		T8	281
valid_sources[0x44]	19763	1		T6	331		T7	1		T8	268
valid_sources[0x45]	18915	1		T5	2		T6	358		T8	317
valid_sources[0x46]	18947	1		T5	1		T6	363		T8	238
valid_sources[0x47]	19779	1		T5	1		T6	356		T8	312
valid_sources[0x48]	20536	1		T6	335		T8	294		T12	204
valid_sources[0x49]	17923	1		T6	327		T8	283		T12	239
valid_sources[0x4a]	19630	1		T5	6		T6	328		T8	327
valid_sources[0x4b]	19258	1		T3	2		T6	369		T8	297
valid_sources[0x4c]	19764	1		T5	1		T6	334		T8	276
valid_sources[0x4d]	20262	1		T6	319		T8	330		T11	2
valid_sources[0x4e]	18728	1		T5	2		T6	308		T7	1
valid_sources[0x4f]	20217	1		T5	2		T6	295		T8	298
valid_sources[0x50]	22159	1		T6	257		T8	256		T11	2
valid_sources[0x51]	20485	1		T5	1		T6	357		T8	291
valid_sources[0x52]	20113	1		T5	4		T6	346		T8	241
valid_sources[0x53]	19744	1		T5	4		T6	366		T8	293
valid_sources[0x54]	21142	1		T6	325		T8	296		T12	249
valid_sources[0x55]	19680	1		T5	2		T6	349		T8	251
valid_sources[0x56]	19652	1		T5	2		T6	323		T8	286
valid_sources[0x57]	18983	1		T6	391		T8	259		T11	1
valid_sources[0x58]	19251	1		T6	354		T8	295		T10	2
valid_sources[0x59]	19459	1		T6	339		T8	268		T11	2
valid_sources[0x5a]	20152	1		T5	2		T6	341		T8	329
valid_sources[0x5b]	19603	1		T6	323		T8	348		T11	1
valid_sources[0x5c]	18233	1		T5	2		T6	302		T8	275
valid_sources[0x5d]	18761	1		T5	1		T6	329		T8	308
valid_sources[0x5e]	18955	1		T6	310		T8	284		T11	3
valid_sources[0x5f]	19384	1		T5	1		T6	375		T8	265
valid_sources[0x60]	19890	1		T2	1		T6	315		T8	309
valid_sources[0x61]	20503	1		T5	1		T6	341		T8	314
valid_sources[0x62]	19395	1		T5	2		T6	306		T8	345
valid_sources[0x63]	19712	1		T6	296		T8	287		T12	211
valid_sources[0x64]	18930	1		T5	1		T6	387		T8	265
valid_sources[0x65]	19569	1		T6	348		T8	308		T12	231
valid_sources[0x66]	21662	1		T5	4		T6	355		T8	296
valid_sources[0x67]	19703	1		T6	334		T8	264		T10	2
valid_sources[0x68]	19801	1		T5	1		T6	363		T8	329
valid_sources[0x69]	18748	1		T5	3		T6	346		T8	292
valid_sources[0x6a]	20151	1		T5	4		T6	271		T7	2
valid_sources[0x6b]	18605	1		T6	364		T8	303		T11	2
valid_sources[0x6c]	19335	1		T6	383		T7	1		T8	336
valid_sources[0x6d]	19417	1		T5	1		T6	388		T8	296
valid_sources[0x6e]	21301	1		T5	3		T6	365		T8	318
valid_sources[0x6f]	18909	1		T5	5		T6	314		T8	289
valid_sources[0x70]	20392	1		T6	348		T8	276		T11	1
valid_sources[0x71]	18771	1		T2	1		T5	1		T6	390
valid_sources[0x72]	18697	1		T6	337		T7	1		T8	264
valid_sources[0x73]	21997	1		T5	4		T6	281		T8	314
valid_sources[0x74]	18142	1		T5	3		T6	332		T8	253
valid_sources[0x75]	18308	1		T5	3		T6	300		T8	255
valid_sources[0x76]	18005	1		T5	1		T6	353		T8	268
valid_sources[0x77]	19795	1		T5	2		T6	349		T7	1
valid_sources[0x78]	19014	1		T5	2		T6	327		T8	278
valid_sources[0x79]	19039	1		T6	382		T8	283		T11	2
valid_sources[0x7a]	19020	1		T2	1		T5	8		T6	350
valid_sources[0x7b]	20998	1		T5	1		T6	289		T8	282
valid_sources[0x7c]	19574	1		T5	2		T6	314		T8	270
valid_sources[0x7d]	21335	1		T5	2		T6	319		T8	281
valid_sources[0x7e]	19830	1		T5	2		T6	248		T8	274
valid_sources[0x7f]	19995	1		T5	5		T6	336		T8	288
valid_sources[0x80]	20222	1		T2	2		T6	363		T8	305

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1158874

1

T1

13

T2

1

T5

14

values[0x0]

all_enables

biggest_size

1744446

1

T1

106

T2

6

T3

7

values[0x1]

all_enables

biggest_size

1745649

1

T1

102

T2

6

T3

5