Toggle Coverage for Module :
prim_onehot_check
| Total | Covered | Percent |
Totals |
5 |
5 |
100.00 |
Total Bits |
36 |
36 |
100.00 |
Total Bits 0->1 |
18 |
18 |
100.00 |
Total Bits 1->0 |
18 |
18 |
100.00 |
| | | |
Ports |
5 |
5 |
100.00 |
Port Bits |
36 |
36 |
100.00 |
Port Bits 0->1 |
18 |
18 |
100.00 |
Port Bits 1->0 |
18 |
18 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T5,T6 |
Yes |
T1,T2,T3 |
INPUT |
oh_i[13:0] |
Yes |
Yes |
T13,T14,T15 |
Yes |
T13,T14,T15 |
INPUT |
addr_i[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
en_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
err_o |
Yes |
Yes |
T13,T14,T15 |
Yes |
T13,T14,T15 |
OUTPUT |