Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	622166704	5514891	0	0
wdog_bark_thold_rd_A	622166704	123655	0	0
wdog_bite_thold_rd_A	622166704	106164	0	0
wdog_ctrl_rd_A	622166704	107197	0	0
wdog_regwen_rd_A	622166704	122745	0	0
wkup_ctrl_rd_A	622166704	107298	0	0
wkup_thold_hi_rd_A	622166704	123841	0	0
wkup_thold_lo_rd_A	622166704	107986	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622166704	5514891	0	0
T6	407169	97722	0	0
T7	15596	0	0	0
T8	319018	71371	0	0
T9	13452	0	0	0
T10	9281	0	0	0
T11	357091	0	0	0
T12	175997	58652	0	0
T22	0	97495	0	0
T27	707222	0	0	0
T36	0	59350	0	0
T37	0	65327	0	0
T38	0	24512	0	0
T39	0	141127	0	0
T40	0	137093	0	0
T41	0	134621	0	0
T42	459558	0	0	0
T43	397000	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622166704	123655	0	0
T6	407169	5049	0	0
T7	15596	0	0	0
T8	319018	7148	0	0
T9	13452	0	0	0
T10	9281	0	0	0
T11	357091	0	0	0
T12	175997	0	0	0
T27	707222	0	0	0
T36	0	3075	0	0
T38	0	1405	0	0
T39	0	7652	0	0
T40	0	14037	0	0
T42	459558	0	0	0
T43	397000	0	0	0
T95	0	11235	0	0
T96	0	7071	0	0
T97	0	9730	0	0
T98	0	6020	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622166704	106164	0	0
T6	407169	4527	0	0
T7	15596	0	0	0
T8	319018	6790	0	0
T9	13452	0	0	0
T10	9281	0	0	0
T11	357091	0	0	0
T12	175997	0	0	0
T27	707222	0	0	0
T36	0	2694	0	0
T38	0	1139	0	0
T39	0	6115	0	0
T40	0	12377	0	0
T42	459558	0	0	0
T43	397000	0	0	0
T95	0	9354	0	0
T96	0	6219	0	0
T97	0	7923	0	0
T98	0	4940	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622166704	107197	0	0
T6	407169	4066	0	0
T7	15596	0	0	0
T8	319018	5911	0	0
T9	13452	0	0	0
T10	9281	0	0	0
T11	357091	0	0	0
T12	175997	0	0	0
T27	707222	0	0	0
T36	0	2639	0	0
T38	0	1287	0	0
T39	0	6322	0	0
T40	0	12080	0	0
T42	459558	0	0	0
T43	397000	0	0	0
T95	0	9634	0	0
T96	0	6237	0	0
T97	0	8850	0	0
T98	0	5201	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622166704	122745	0	0
T6	407169	5017	0	0
T7	15596	0	0	0
T8	319018	7321	0	0
T9	13452	0	0	0
T10	9281	0	0	0
T11	357091	0	0	0
T12	175997	0	0	0
T27	707222	0	0	0
T36	0	2874	0	0
T38	0	1304	0	0
T39	0	7378	0	0
T40	0	13625	0	0
T42	459558	0	0	0
T43	397000	0	0	0
T95	0	11029	0	0
T96	0	7167	0	0
T97	0	9463	0	0
T98	0	5533	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622166704	107298	0	0
T6	407169	4277	0	0
T7	15596	0	0	0
T8	319018	6659	0	0
T9	13452	0	0	0
T10	9281	0	0	0
T11	357091	0	0	0
T12	175997	0	0	0
T27	707222	0	0	0
T36	0	2703	0	0
T38	0	1389	0	0
T39	0	6110	0	0
T40	0	12343	0	0
T42	459558	0	0	0
T43	397000	0	0	0
T95	0	9421	0	0
T96	0	5929	0	0
T97	0	8595	0	0
T98	0	4922	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622166704	123841	0	0
T6	407169	4806	0	0
T7	15596	0	0	0
T8	319018	7485	0	0
T9	13452	0	0	0
T10	9281	0	0	0
T11	357091	0	0	0
T12	175997	0	0	0
T27	707222	0	0	0
T36	0	3059	0	0
T38	0	1410	0	0
T39	0	7245	0	0
T40	0	14177	0	0
T42	459558	0	0	0
T43	397000	0	0	0
T95	0	10689	0	0
T96	0	7042	0	0
T97	0	9781	0	0
T98	0	5895	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622166704	107986	0	0
T6	407169	4172	0	0
T7	15596	0	0	0
T8	319018	6336	0	0
T9	13452	0	0	0
T10	9281	0	0	0
T11	357091	0	0	0
T12	175997	0	0	0
T27	707222	0	0	0
T36	0	2767	0	0
T38	0	1340	0	0
T39	0	6155	0	0
T40	0	12403	0	0
T42	459558	0	0	0
T43	397000	0	0	0
T95	0	9834	0	0
T96	0	5999	0	0
T97	0	8777	0	0
T98	0	5105	0	0