Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	437294	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5441174	1		T1	159444		T2	225		T3	79241

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1442714	1		T1	42246		T2	41		T3	21128
values[0x0]	2078480	1		T1	60761		T2	161		T3	30309
values[0x1]	2357274	1		T1	69225		T2	134		T3	34591

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	193174	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5685294	1		T1	166666		T2	247		T3	83059

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23279	1		T1	676		T2	1		T3	404
valid_sources[0x01]	22786	1		T1	665		T2	1		T3	349
valid_sources[0x02]	24282	1		T1	619		T2	2		T3	353
valid_sources[0x03]	21615	1		T1	652		T3	355		T5	3
valid_sources[0x04]	22005	1		T1	706		T2	1		T3	357
valid_sources[0x05]	23949	1		T1	614		T2	1		T3	305
valid_sources[0x06]	23162	1		T1	656		T2	1		T3	325
valid_sources[0x07]	22827	1		T1	670		T3	331		T4	1
valid_sources[0x08]	23799	1		T1	666		T3	317		T5	2
valid_sources[0x09]	23509	1		T1	666		T2	1		T3	358
valid_sources[0x0a]	23540	1		T1	621		T2	1		T3	272
valid_sources[0x0b]	24129	1		T1	661		T3	344		T5	1
valid_sources[0x0c]	23081	1		T1	652		T2	1		T3	362
valid_sources[0x0d]	23469	1		T1	706		T2	1		T3	356
valid_sources[0x0e]	22765	1		T1	673		T3	315		T4	3
valid_sources[0x0f]	23470	1		T1	693		T3	355		T5	2
valid_sources[0x10]	23414	1		T1	665		T3	329		T5	2
valid_sources[0x11]	21928	1		T1	643		T3	357		T5	1
valid_sources[0x12]	22413	1		T1	618		T3	314		T4	1
valid_sources[0x13]	23230	1		T1	673		T2	1		T3	286
valid_sources[0x14]	22266	1		T1	688		T2	4		T3	328
valid_sources[0x15]	23366	1		T1	687		T2	1		T3	339
valid_sources[0x16]	22545	1		T1	681		T3	323		T4	7
valid_sources[0x17]	23429	1		T1	715		T2	2		T3	312
valid_sources[0x18]	22745	1		T1	759		T2	2		T3	301
valid_sources[0x19]	23077	1		T1	689		T3	324		T4	4
valid_sources[0x1a]	22748	1		T1	667		T2	5		T3	351
valid_sources[0x1b]	21981	1		T1	700		T2	2		T3	334
valid_sources[0x1c]	24185	1		T1	637		T3	381		T4	2
valid_sources[0x1d]	21627	1		T1	696		T2	1		T3	312
valid_sources[0x1e]	22505	1		T1	706		T2	3		T3	329
valid_sources[0x1f]	22756	1		T1	688		T3	358		T5	2
valid_sources[0x20]	23502	1		T1	679		T2	2		T3	344
valid_sources[0x21]	23894	1		T1	659		T3	322		T5	1
valid_sources[0x22]	22632	1		T1	640		T2	2		T3	347
valid_sources[0x23]	23246	1		T1	713		T2	1		T3	338
valid_sources[0x24]	21841	1		T1	648		T2	1		T3	348
valid_sources[0x25]	23301	1		T1	693		T2	2		T3	361
valid_sources[0x26]	23799	1		T1	720		T2	2		T3	339
valid_sources[0x27]	24087	1		T1	668		T2	2		T3	345
valid_sources[0x28]	24209	1		T1	617		T2	1		T3	345
valid_sources[0x29]	22763	1		T1	697		T3	314		T4	1
valid_sources[0x2a]	22994	1		T1	619		T2	2		T3	328
valid_sources[0x2b]	22588	1		T1	609		T2	2		T3	313
valid_sources[0x2c]	23136	1		T1	703		T2	1		T3	339
valid_sources[0x2d]	22004	1		T1	647		T3	317		T4	2
valid_sources[0x2e]	23945	1		T1	644		T2	4		T3	341
valid_sources[0x2f]	23369	1		T1	697		T3	344		T5	1
valid_sources[0x30]	23140	1		T1	708		T2	1		T3	327
valid_sources[0x31]	22050	1		T1	661		T3	360		T9	385
valid_sources[0x32]	22501	1		T1	697		T3	297		T6	1
valid_sources[0x33]	22044	1		T1	719		T2	1		T3	344
valid_sources[0x34]	22515	1		T1	727		T2	6		T3	330
valid_sources[0x35]	22091	1		T1	649		T2	1		T3	312
valid_sources[0x36]	23035	1		T1	679		T2	2		T3	331
valid_sources[0x37]	23993	1		T1	690		T3	367		T4	1
valid_sources[0x38]	22749	1		T1	672		T2	1		T3	338
valid_sources[0x39]	23354	1		T1	647		T2	1		T3	338
valid_sources[0x3a]	22463	1		T1	666		T2	1		T3	317
valid_sources[0x3b]	22350	1		T1	672		T2	6		T3	352
valid_sources[0x3c]	23729	1		T1	713		T2	3		T3	321
valid_sources[0x3d]	23006	1		T1	722		T2	2		T3	350
valid_sources[0x3e]	21481	1		T1	649		T2	2		T3	312
valid_sources[0x3f]	24140	1		T1	672		T3	370		T4	5
valid_sources[0x40]	23193	1		T1	731		T2	4		T3	341
valid_sources[0x41]	24043	1		T1	676		T2	4		T3	311
valid_sources[0x42]	23385	1		T1	698		T2	1		T3	318
valid_sources[0x43]	24382	1		T1	661		T2	3		T3	276
valid_sources[0x44]	21784	1		T1	660		T2	3		T3	319
valid_sources[0x45]	22871	1		T1	617		T2	2		T3	336
valid_sources[0x46]	22787	1		T1	659		T2	3		T3	323
valid_sources[0x47]	21530	1		T1	682		T3	322		T7	3
valid_sources[0x48]	22917	1		T1	719		T2	1		T3	297
valid_sources[0x49]	23816	1		T1	688		T2	2		T3	330
valid_sources[0x4a]	23002	1		T1	699		T2	1		T3	298
valid_sources[0x4b]	23308	1		T1	687		T2	1		T3	381
valid_sources[0x4c]	21756	1		T1	616		T2	1		T3	349
valid_sources[0x4d]	21753	1		T1	744		T3	367		T4	1
valid_sources[0x4e]	23329	1		T1	671		T3	310		T5	3
valid_sources[0x4f]	25221	1		T1	676		T2	2		T3	347
valid_sources[0x50]	22365	1		T1	664		T2	2		T3	352
valid_sources[0x51]	21968	1		T1	684		T3	371		T4	1
valid_sources[0x52]	22803	1		T1	709		T2	1		T3	297
valid_sources[0x53]	23129	1		T1	692		T3	351		T5	4
valid_sources[0x54]	22639	1		T1	673		T3	303		T9	421
valid_sources[0x55]	23550	1		T1	683		T2	1		T3	325
valid_sources[0x56]	24570	1		T1	666		T3	316		T9	363
valid_sources[0x57]	22344	1		T1	709		T2	1		T3	353
valid_sources[0x58]	22755	1		T1	683		T3	364		T5	1
valid_sources[0x59]	22566	1		T1	653		T2	1		T3	341
valid_sources[0x5a]	23296	1		T1	658		T2	2		T3	302
valid_sources[0x5b]	22173	1		T1	633		T2	1		T3	360
valid_sources[0x5c]	23284	1		T1	687		T2	2		T3	319
valid_sources[0x5d]	22613	1		T1	697		T3	344		T5	2
valid_sources[0x5e]	22639	1		T1	703		T2	1		T3	369
valid_sources[0x5f]	23143	1		T1	706		T2	4		T3	314
valid_sources[0x60]	26341	1		T1	716		T3	339		T5	3
valid_sources[0x61]	22715	1		T1	623		T2	2		T3	321
valid_sources[0x62]	22493	1		T1	690		T2	1		T3	332
valid_sources[0x63]	22405	1		T1	651		T3	340		T4	5
valid_sources[0x64]	22360	1		T1	695		T2	2		T3	336
valid_sources[0x65]	22449	1		T1	672		T2	2		T3	393
valid_sources[0x66]	24402	1		T1	638		T3	327		T5	2
valid_sources[0x67]	22977	1		T1	690		T3	355		T5	3
valid_sources[0x68]	23432	1		T1	665		T2	2		T3	305
valid_sources[0x69]	23807	1		T1	703		T2	4		T3	355
valid_sources[0x6a]	21488	1		T1	658		T2	2		T3	339
valid_sources[0x6b]	22192	1		T1	623		T2	3		T3	323
valid_sources[0x6c]	23682	1		T1	675		T3	333		T9	408
valid_sources[0x6d]	22011	1		T1	672		T2	2		T3	325
valid_sources[0x6e]	22587	1		T1	614		T3	330		T9	406
valid_sources[0x6f]	21234	1		T1	685		T3	371		T5	3
valid_sources[0x70]	22591	1		T1	652		T2	1		T3	353
valid_sources[0x71]	23406	1		T1	732		T2	1		T3	335
valid_sources[0x72]	21780	1		T1	652		T3	338		T5	1
valid_sources[0x73]	22228	1		T1	616		T2	2		T3	381
valid_sources[0x74]	24054	1		T1	698		T2	1		T3	376
valid_sources[0x75]	22950	1		T1	629		T2	2		T3	320
valid_sources[0x76]	21953	1		T1	679		T2	3		T3	306
valid_sources[0x77]	23230	1		T1	637		T3	352		T7	2
valid_sources[0x78]	21609	1		T1	633		T2	1		T3	336
valid_sources[0x79]	21992	1		T1	647		T2	2		T3	328
valid_sources[0x7a]	22128	1		T1	588		T3	348		T5	3
valid_sources[0x7b]	22442	1		T1	708		T2	1		T3	345
valid_sources[0x7c]	21996	1		T1	671		T2	2		T3	372
valid_sources[0x7d]	24489	1		T1	691		T3	334		T5	4
valid_sources[0x7e]	23509	1		T1	669		T2	1		T3	336
valid_sources[0x7f]	23045	1		T1	705		T2	3		T3	360
valid_sources[0x80]	22210	1		T1	688		T2	1		T3	353

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1355245

1

T1

39786

T2

19

T3

19739

values[0x0]

all_enables

biggest_size

2042506

1

T1

59743

T2

109

T3

29815

values[0x1]

all_enables

biggest_size

2043423

1

T1

59915

T2

97

T3

29687