Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	609768096	6406751	0	0
wdog_bark_thold_rd_A	609768096	118193	0	0
wdog_bite_thold_rd_A	609768096	104172	0	0
wdog_ctrl_rd_A	609768096	105361	0	0
wdog_regwen_rd_A	609768096	120094	0	0
wkup_ctrl_rd_A	609768096	105638	0	0
wkup_thold_hi_rd_A	609768096	119995	0	0
wkup_thold_lo_rd_A	609768096	105809	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609768096	6406751	0	0
T1	769296	191894	0	0
T2	309656	0	0	0
T3	391038	103512	0	0
T4	782420	0	0	0
T5	123791	0	0	0
T6	21126	0	0	0
T7	547917	0	0	0
T8	120310	0	0	0
T9	661093	115789	0	0
T10	233714	0	0	0
T11	0	33655	0	0
T21	0	195837	0	0
T27	0	6212	0	0
T38	0	314137	0	0
T39	0	215284	0	0
T40	0	46824	0	0
T41	0	47424	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609768096	118193	0	0
T27	462575	874	0	0
T28	8401	0	0	0
T33	5098	0	0	0
T39	0	20528	0	0
T40	0	4522	0	0
T42	7547	0	0	0
T43	339227	0	0	0
T44	243283	0	0	0
T45	640569	0	0	0
T57	0	7271	0	0
T76	9362	0	0	0
T78	0	12471	0	0
T80	0	25564	0	0
T81	0	6134	0	0
T82	0	8338	0	0
T83	0	3879	0	0
T84	0	4683	0	0
T85	360958	0	0	0
T86	44206	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609768096	104172	0	0
T27	462575	678	0	0
T28	8401	0	0	0
T33	5098	0	0	0
T39	0	18566	0	0
T40	0	3704	0	0
T42	7547	0	0	0
T43	339227	0	0	0
T44	243283	0	0	0
T45	640569	0	0	0
T57	0	6186	0	0
T76	9362	0	0	0
T78	0	10974	0	0
T80	0	22287	0	0
T81	0	5016	0	0
T82	0	7470	0	0
T83	0	3543	0	0
T84	0	4113	0	0
T85	360958	0	0	0
T86	44206	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609768096	105361	0	0
T27	462575	653	0	0
T28	8401	0	0	0
T33	5098	0	0	0
T39	0	18141	0	0
T40	0	3859	0	0
T42	7547	0	0	0
T43	339227	0	0	0
T44	243283	0	0	0
T45	640569	0	0	0
T57	0	6020	0	0
T76	9362	0	0	0
T78	0	11161	0	0
T80	0	23048	0	0
T81	0	5136	0	0
T82	0	7296	0	0
T83	0	3792	0	0
T84	0	4140	0	0
T85	360958	0	0	0
T86	44206	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609768096	120094	0	0
T27	462575	716	0	0
T28	8401	0	0	0
T33	5098	0	0	0
T39	0	21528	0	0
T40	0	4467	0	0
T42	7547	0	0	0
T43	339227	0	0	0
T44	243283	0	0	0
T45	640569	0	0	0
T57	0	7503	0	0
T76	9362	0	0	0
T78	0	12210	0	0
T80	0	25201	0	0
T81	0	5834	0	0
T82	0	8419	0	0
T83	0	4388	0	0
T84	0	5032	0	0
T85	360958	0	0	0
T86	44206	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609768096	105638	0	0
T27	462575	880	0	0
T28	8401	0	0	0
T33	5098	0	0	0
T39	0	18997	0	0
T40	0	3979	0	0
T42	7547	0	0	0
T43	339227	0	0	0
T44	243283	0	0	0
T45	640569	0	0	0
T57	0	5905	0	0
T76	9362	0	0	0
T78	0	10917	0	0
T80	0	22737	0	0
T81	0	5337	0	0
T82	0	7069	0	0
T83	0	3782	0	0
T84	0	4201	0	0
T85	360958	0	0	0
T86	44206	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609768096	119995	0	0
T27	462575	784	0	0
T28	8401	0	0	0
T33	5098	0	0	0
T39	0	21236	0	0
T40	0	4865	0	0
T42	7547	0	0	0
T43	339227	0	0	0
T44	243283	0	0	0
T45	640569	0	0	0
T57	0	7178	0	0
T76	9362	0	0	0
T78	0	12310	0	0
T80	0	25959	0	0
T81	0	5820	0	0
T82	0	8311	0	0
T83	0	4194	0	0
T84	0	4993	0	0
T85	360958	0	0	0
T86	44206	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	609768096	105809	0	0
T27	462575	703	0	0
T28	8401	0	0	0
T33	5098	0	0	0
T39	0	19182	0	0
T40	0	3833	0	0
T42	7547	0	0	0
T43	339227	0	0	0
T44	243283	0	0	0
T45	640569	0	0	0
T57	0	6168	0	0
T76	9362	0	0	0
T78	0	11218	0	0
T80	0	22788	0	0
T81	0	4985	0	0
T82	0	7823	0	0
T83	0	3388	0	0
T84	0	4281	0	0
T85	360958	0	0	0
T86	44206	0	0	0