Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	345992	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4242302	1		T1	15		T2	13		T3	18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1126753	1		T1	1		T2	1		T3	1
values[0x0]	1623730	1		T1	12		T2	8		T3	10
values[0x1]	1837811	1		T1	6		T2	11		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154219	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4434075	1		T1	15		T2	15		T3	18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17879	1		T4	207		T5	768		T6	73
valid_sources[0x01]	17560	1		T4	194		T5	909		T6	171
valid_sources[0x02]	17695	1		T4	189		T5	763		T6	231
valid_sources[0x03]	16666	1		T4	185		T5	795		T6	223
valid_sources[0x04]	17492	1		T4	186		T5	763		T6	19
valid_sources[0x05]	18658	1		T4	258		T5	850		T6	194
valid_sources[0x06]	18096	1		T4	225		T5	843		T6	188
valid_sources[0x07]	17509	1		T4	216		T5	771		T6	151
valid_sources[0x08]	17686	1		T4	204		T5	689		T6	241
valid_sources[0x09]	16707	1		T4	216		T5	671		T6	21
valid_sources[0x0a]	17455	1		T4	204		T5	714		T6	11
valid_sources[0x0b]	18975	1		T3	1		T4	186		T5	794
valid_sources[0x0c]	18726	1		T3	1		T4	199		T5	719
valid_sources[0x0d]	18146	1		T4	194		T5	757		T6	220
valid_sources[0x0e]	16527	1		T4	219		T5	733		T6	263
valid_sources[0x0f]	17132	1		T4	222		T5	726		T6	121
valid_sources[0x10]	17722	1		T4	207		T5	801		T6	354
valid_sources[0x11]	19012	1		T3	1		T4	217		T5	866
valid_sources[0x12]	18125	1		T4	216		T5	710		T6	26
valid_sources[0x13]	17575	1		T4	196		T5	912		T6	30
valid_sources[0x14]	17612	1		T4	221		T5	754		T6	110
valid_sources[0x15]	17199	1		T4	172		T5	839		T6	119
valid_sources[0x16]	18359	1		T4	182		T5	816		T6	102
valid_sources[0x17]	17737	1		T4	178		T5	785		T6	307
valid_sources[0x18]	17780	1		T4	180		T5	815		T6	71
valid_sources[0x19]	17588	1		T4	196		T5	797		T6	67
valid_sources[0x1a]	16415	1		T4	187		T5	764		T6	25
valid_sources[0x1b]	17426	1		T4	202		T5	869		T6	217
valid_sources[0x1c]	17585	1		T4	204		T5	842		T6	325
valid_sources[0x1d]	16463	1		T3	1		T4	188		T5	717
valid_sources[0x1e]	18415	1		T4	216		T5	730		T6	213
valid_sources[0x1f]	18744	1		T4	205		T5	798		T6	7
valid_sources[0x20]	16986	1		T4	185		T5	648		T6	377
valid_sources[0x21]	18806	1		T4	241		T5	730		T6	259
valid_sources[0x22]	18013	1		T4	233		T5	784		T6	358
valid_sources[0x23]	17932	1		T4	191		T5	747		T6	354
valid_sources[0x24]	16695	1		T4	221		T5	784		T6	43
valid_sources[0x25]	19299	1		T4	239		T5	775		T6	384
valid_sources[0x26]	17279	1		T3	1		T4	178		T5	709
valid_sources[0x27]	17740	1		T4	216		T5	736		T6	156
valid_sources[0x28]	17561	1		T4	229		T5	675		T6	366
valid_sources[0x29]	16923	1		T4	197		T5	798		T6	220
valid_sources[0x2a]	17596	1		T4	184		T5	789		T6	73
valid_sources[0x2b]	18836	1		T4	172		T5	716		T6	99
valid_sources[0x2c]	19199	1		T4	187		T5	822		T6	241
valid_sources[0x2d]	17724	1		T4	200		T5	818		T6	99
valid_sources[0x2e]	17235	1		T4	186		T5	805		T6	100
valid_sources[0x2f]	18462	1		T4	185		T5	700		T6	314
valid_sources[0x30]	17303	1		T4	211		T5	785		T6	98
valid_sources[0x31]	18345	1		T4	176		T5	729		T6	284
valid_sources[0x32]	18267	1		T4	166		T5	688		T6	106
valid_sources[0x33]	18677	1		T4	230		T5	862		T6	349
valid_sources[0x34]	17633	1		T4	194		T5	672		T6	20
valid_sources[0x35]	18089	1		T4	209		T5	722		T6	304
valid_sources[0x36]	18842	1		T4	215		T5	827		T6	239
valid_sources[0x37]	18941	1		T4	193		T5	741		T6	460
valid_sources[0x38]	20364	1		T4	246		T5	832		T6	385
valid_sources[0x39]	18958	1		T4	218		T5	729		T6	331
valid_sources[0x3a]	17755	1		T4	214		T5	808		T6	479
valid_sources[0x3b]	17845	1		T4	182		T5	741		T6	97
valid_sources[0x3c]	17393	1		T4	195		T5	855		T6	53
valid_sources[0x3d]	17968	1		T4	249		T5	780		T6	415
valid_sources[0x3e]	19394	1		T4	188		T5	776		T6	778
valid_sources[0x3f]	17209	1		T4	207		T5	818		T6	191
valid_sources[0x40]	18435	1		T4	182		T5	649		T6	321
valid_sources[0x41]	17483	1		T4	195		T5	740		T6	304
valid_sources[0x42]	18258	1		T4	211		T5	703		T6	464
valid_sources[0x43]	18137	1		T1	19		T4	223		T5	728
valid_sources[0x44]	16974	1		T4	251		T5	727		T6	36
valid_sources[0x45]	17856	1		T4	184		T5	718		T6	265
valid_sources[0x46]	17919	1		T4	242		T5	825		T6	125
valid_sources[0x47]	16851	1		T4	170		T5	815		T6	291
valid_sources[0x48]	17998	1		T4	212		T5	734		T6	277
valid_sources[0x49]	19806	1		T4	228		T5	825		T6	34
valid_sources[0x4a]	17089	1		T4	210		T5	833		T6	247
valid_sources[0x4b]	17066	1		T4	217		T5	749		T6	69
valid_sources[0x4c]	17435	1		T4	210		T5	694		T6	631
valid_sources[0x4d]	18175	1		T4	195		T5	761		T6	149
valid_sources[0x4e]	17452	1		T4	206		T5	824		T6	288
valid_sources[0x4f]	17507	1		T4	223		T5	726		T6	12
valid_sources[0x50]	20005	1		T4	232		T5	858		T6	153
valid_sources[0x51]	17074	1		T4	199		T5	773		T6	17
valid_sources[0x52]	18216	1		T4	205		T5	937		T6	387
valid_sources[0x53]	17201	1		T4	194		T5	796		T6	198
valid_sources[0x54]	18281	1		T4	211		T5	773		T6	132
valid_sources[0x55]	18143	1		T4	207		T5	756		T6	297
valid_sources[0x56]	17395	1		T4	201		T5	739		T6	46
valid_sources[0x57]	17811	1		T4	190		T5	742		T6	62
valid_sources[0x58]	17865	1		T4	205		T5	834		T6	301
valid_sources[0x59]	17195	1		T4	212		T5	773		T6	14
valid_sources[0x5a]	17046	1		T4	234		T5	785		T6	206
valid_sources[0x5b]	18312	1		T4	176		T5	771		T6	203
valid_sources[0x5c]	17564	1		T4	199		T5	696		T6	224
valid_sources[0x5d]	18053	1		T3	1		T4	157		T5	801
valid_sources[0x5e]	17851	1		T4	182		T5	775		T6	213
valid_sources[0x5f]	18909	1		T4	243		T5	862		T6	229
valid_sources[0x60]	18477	1		T4	205		T5	691		T6	711
valid_sources[0x61]	17986	1		T4	227		T5	715		T6	14
valid_sources[0x62]	17766	1		T4	179		T5	908		T6	27
valid_sources[0x63]	18576	1		T4	205		T5	680		T6	367
valid_sources[0x64]	17791	1		T4	230		T5	725		T6	265
valid_sources[0x65]	18464	1		T4	171		T5	748		T6	171
valid_sources[0x66]	17957	1		T4	188		T5	825		T6	40
valid_sources[0x67]	17902	1		T4	195		T5	826		T6	538
valid_sources[0x68]	17745	1		T4	197		T5	792		T6	64
valid_sources[0x69]	19718	1		T4	195		T5	738		T6	821
valid_sources[0x6a]	17675	1		T4	181		T5	733		T6	528
valid_sources[0x6b]	17403	1		T4	199		T5	782		T6	149
valid_sources[0x6c]	17162	1		T4	198		T5	755		T6	24
valid_sources[0x6d]	18032	1		T4	168		T5	745		T6	242
valid_sources[0x6e]	18363	1		T4	272		T5	787		T6	617
valid_sources[0x6f]	19157	1		T4	235		T5	743		T6	249
valid_sources[0x70]	18368	1		T4	185		T5	804		T6	219
valid_sources[0x71]	17870	1		T4	174		T5	694		T6	13
valid_sources[0x72]	17519	1		T4	209		T5	784		T6	700
valid_sources[0x73]	17641	1		T3	1		T4	177		T5	827
valid_sources[0x74]	17911	1		T4	190		T5	741		T6	222
valid_sources[0x75]	18047	1		T3	1		T4	182		T5	848
valid_sources[0x76]	17700	1		T3	1		T4	231		T5	697
valid_sources[0x77]	17074	1		T4	213		T5	835		T6	120
valid_sources[0x78]	17894	1		T4	215		T5	846		T6	294
valid_sources[0x79]	17776	1		T3	1		T4	226		T5	869
valid_sources[0x7a]	18905	1		T4	191		T5	792		T6	33
valid_sources[0x7b]	17590	1		T4	190		T5	699		T6	533
valid_sources[0x7c]	17533	1		T4	204		T5	785		T6	81
valid_sources[0x7d]	17174	1		T3	1		T4	194		T5	738
valid_sources[0x7e]	18723	1		T4	203		T5	858		T6	157
valid_sources[0x7f]	18201	1		T4	215		T5	781		T6	154
valid_sources[0x80]	17982	1		T3	1		T4	201		T5	788

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1057373

1

T1

1

T3

1

T4

12194

values[0x0]

all_enables

biggest_size

1594375

1

T1

8

T2

5

T3

8

values[0x1]

all_enables

biggest_size

1590554

1

T1

6

T2

8

T3

9