Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	659285276	5012644	0	0
wdog_bark_thold_rd_A	659285276	121355	0	0
wdog_bite_thold_rd_A	659285276	107635	0	0
wdog_ctrl_rd_A	659285276	106297	0	0
wdog_regwen_rd_A	659285276	120713	0	0
wkup_ctrl_rd_A	659285276	105422	0	0
wkup_thold_hi_rd_A	659285276	121377	0	0
wkup_thold_lo_rd_A	659285276	106589	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659285276	5012644	0	0
T4	155809	54211	0	0
T5	102789	224859	0	0
T6	519592	60130	0	0
T7	658630	0	0	0
T8	167959	0	0	0
T9	15014	0	0	0
T10	37584	0	0	0
T11	115818	0	0	0
T21	0	78733	0	0
T24	0	148897	0	0
T30	33223	0	0	0
T31	42090	0	0	0
T32	0	141424	0	0
T37	0	58619	0	0
T44	0	282778	0	0
T45	0	80860	0	0
T46	0	152432	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659285276	121355	0	0
T6	519592	6050	0	0
T7	658630	0	0	0
T8	167959	0	0	0
T9	15014	0	0	0
T10	37584	0	0	0
T11	115818	0	0	0
T12	217833	0	0	0
T13	89996	0	0	0
T30	33223	0	0	0
T31	42090	0	0	0
T32	0	14531	0	0
T37	0	5617	0	0
T45	0	3974	0	0
T84	0	11283	0	0
T85	0	1076	0	0
T86	0	9175	0	0
T87	0	9134	0	0
T88	0	3512	0	0
T89	0	19155	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659285276	107635	0	0
T6	519592	5378	0	0
T7	658630	0	0	0
T8	167959	0	0	0
T9	15014	0	0	0
T10	37584	0	0	0
T11	115818	0	0	0
T12	217833	0	0	0
T13	89996	0	0	0
T30	33223	0	0	0
T31	42090	0	0	0
T32	0	12817	0	0
T37	0	5182	0	0
T45	0	3679	0	0
T84	0	10404	0	0
T85	0	993	0	0
T86	0	7998	0	0
T87	0	8314	0	0
T88	0	2904	0	0
T89	0	16595	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659285276	106297	0	0
T6	519592	5146	0	0
T7	658630	0	0	0
T8	167959	0	0	0
T9	15014	0	0	0
T10	37584	0	0	0
T11	115818	0	0	0
T12	217833	0	0	0
T13	89996	0	0	0
T30	33223	0	0	0
T31	42090	0	0	0
T32	0	12259	0	0
T37	0	5040	0	0
T45	0	3726	0	0
T84	0	10209	0	0
T85	0	1104	0	0
T86	0	7589	0	0
T87	0	8101	0	0
T88	0	2723	0	0
T89	0	16524	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659285276	120713	0	0
T6	519592	5770	0	0
T7	658630	0	0	0
T8	167959	0	0	0
T9	15014	0	0	0
T10	37584	0	0	0
T11	115818	0	0	0
T12	217833	0	0	0
T13	89996	0	0	0
T30	33223	0	0	0
T31	42090	0	0	0
T32	0	14564	0	0
T37	0	5858	0	0
T45	0	4536	0	0
T84	0	11662	0	0
T85	0	1343	0	0
T86	0	8771	0	0
T87	0	8947	0	0
T88	0	3116	0	0
T89	0	18407	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659285276	105422	0	0
T6	519592	5360	0	0
T7	658630	0	0	0
T8	167959	0	0	0
T9	15014	0	0	0
T10	37584	0	0	0
T11	115818	0	0	0
T12	217833	0	0	0
T13	89996	0	0	0
T30	33223	0	0	0
T31	42090	0	0	0
T32	0	12800	0	0
T37	0	4930	0	0
T45	0	3643	0	0
T84	0	9997	0	0
T85	0	885	0	0
T86	0	7861	0	0
T87	0	8140	0	0
T88	0	2703	0	0
T89	0	16181	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659285276	121377	0	0
T6	519592	6167	0	0
T7	658630	0	0	0
T8	167959	0	0	0
T9	15014	0	0	0
T10	37584	0	0	0
T11	115818	0	0	0
T12	217833	0	0	0
T13	89996	0	0	0
T30	33223	0	0	0
T31	42090	0	0	0
T32	0	14005	0	0
T37	0	5612	0	0
T45	0	4132	0	0
T84	0	11844	0	0
T85	0	1108	0	0
T86	0	8734	0	0
T87	0	9405	0	0
T88	0	3387	0	0
T89	0	18626	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659285276	106589	0	0
T6	519592	5399	0	0
T7	658630	0	0	0
T8	167959	0	0	0
T9	15014	0	0	0
T10	37584	0	0	0
T11	115818	0	0	0
T12	217833	0	0	0
T13	89996	0	0	0
T30	33223	0	0	0
T31	42090	0	0	0
T32	0	12828	0	0
T37	0	4984	0	0
T45	0	3674	0	0
T84	0	10054	0	0
T85	0	1075	0	0
T86	0	7568	0	0
T87	0	8547	0	0
T88	0	3091	0	0
T89	0	15977	0	0