Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	403701	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5003489	1		T1	229		T2	16		T3	218

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1329020	1		T1	56		T2	1		T3	43
values[0x0]	1910765	1		T1	140		T2	10		T3	136
values[0x1]	2167405	1		T1	148		T2	11		T3	152

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	179677	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5227513	1		T1	261		T2	17		T3	242

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20257	1		T7	1		T13	1		T17	528
valid_sources[0x01]	20649	1		T3	3		T9	1		T12	19
valid_sources[0x02]	20990	1		T13	3		T14	1		T17	1248
valid_sources[0x03]	21424	1		T11	1		T13	2		T17	1275
valid_sources[0x04]	21313	1		T3	1		T13	2		T14	2
valid_sources[0x05]	19923	1		T13	2		T17	1039		T26	1
valid_sources[0x06]	20656	1		T1	17		T13	5		T14	1
valid_sources[0x07]	20903	1		T2	1		T3	3		T13	2
valid_sources[0x08]	22428	1		T3	1		T14	1		T17	922
valid_sources[0x09]	20177	1		T3	2		T13	1		T14	2
valid_sources[0x0a]	21986	1		T3	1		T13	1		T14	4
valid_sources[0x0b]	21105	1		T13	1		T14	1		T17	1167
valid_sources[0x0c]	22343	1		T3	1		T13	1		T14	1
valid_sources[0x0d]	19808	1		T14	1		T17	110		T26	2
valid_sources[0x0e]	20443	1		T13	3		T17	398		T26	1
valid_sources[0x0f]	22348	1		T13	1		T14	3		T17	324
valid_sources[0x10]	20859	1		T17	707		T19	564		T20	396
valid_sources[0x11]	20469	1		T9	1		T14	3		T17	808
valid_sources[0x12]	20471	1		T13	2		T14	1		T17	635
valid_sources[0x13]	20910	1		T3	2		T9	2		T12	18
valid_sources[0x14]	21997	1		T13	1		T17	1448		T26	1
valid_sources[0x15]	20805	1		T7	1		T13	1		T25	3
valid_sources[0x16]	20593	1		T12	5		T13	1		T17	578
valid_sources[0x17]	21155	1		T3	1		T12	5		T13	2
valid_sources[0x18]	22514	1		T3	2		T5	3		T14	1
valid_sources[0x19]	20094	1		T3	1		T13	3		T17	299
valid_sources[0x1a]	21730	1		T13	1		T14	1		T15	1
valid_sources[0x1b]	21220	1		T1	1		T14	1		T17	862
valid_sources[0x1c]	22048	1		T3	1		T13	3		T14	1
valid_sources[0x1d]	20466	1		T3	1		T11	8		T13	1
valid_sources[0x1e]	21830	1		T1	3		T5	5		T6	4
valid_sources[0x1f]	20872	1		T3	2		T13	2		T25	1
valid_sources[0x20]	22047	1		T3	5		T14	3		T17	660
valid_sources[0x21]	20419	1		T1	3		T12	17		T17	1276
valid_sources[0x22]	22028	1		T3	3		T7	1		T13	2
valid_sources[0x23]	20923	1		T13	2		T14	3		T17	500
valid_sources[0x24]	19827	1		T1	6		T7	1		T13	1
valid_sources[0x25]	21033	1		T1	31		T13	2		T14	1
valid_sources[0x26]	21155	1		T3	2		T14	1		T15	2
valid_sources[0x27]	20959	1		T3	4		T7	1		T14	3
valid_sources[0x28]	20808	1		T3	2		T13	2		T14	1
valid_sources[0x29]	20183	1		T14	1		T17	924		T26	3
valid_sources[0x2a]	20524	1		T3	1		T13	1		T17	518
valid_sources[0x2b]	20019	1		T3	2		T11	1		T13	1
valid_sources[0x2c]	22099	1		T3	1		T14	2		T15	1
valid_sources[0x2d]	22474	1		T3	4		T13	2		T17	976
valid_sources[0x2e]	21102	1		T3	2		T13	4		T14	1
valid_sources[0x2f]	20366	1		T3	2		T13	1		T14	1
valid_sources[0x30]	21537	1		T1	23		T4	22		T25	1
valid_sources[0x31]	20310	1		T3	1		T13	1		T17	346
valid_sources[0x32]	20809	1		T2	1		T3	1		T13	1
valid_sources[0x33]	21542	1		T2	1		T12	5		T14	2
valid_sources[0x34]	21520	1		T7	1		T10	20		T12	1
valid_sources[0x35]	20432	1		T1	8		T3	2		T14	2
valid_sources[0x36]	22224	1		T14	2		T15	2		T17	1418
valid_sources[0x37]	19989	1		T3	2		T14	1		T17	825
valid_sources[0x38]	21490	1		T14	2		T17	594		T19	1247
valid_sources[0x39]	21709	1		T3	3		T9	1		T13	3
valid_sources[0x3a]	21010	1		T2	1		T12	2		T13	2
valid_sources[0x3b]	22653	1		T3	4		T13	2		T14	4
valid_sources[0x3c]	22179	1		T3	1		T14	1		T17	963
valid_sources[0x3d]	20740	1		T3	2		T9	1		T12	9
valid_sources[0x3e]	20363	1		T2	1		T3	5		T13	2
valid_sources[0x3f]	21598	1		T3	1		T14	2		T17	559
valid_sources[0x40]	21776	1		T1	14		T13	1		T17	1471
valid_sources[0x41]	22432	1		T14	2		T17	686		T26	2
valid_sources[0x42]	21259	1		T3	1		T13	4		T14	1
valid_sources[0x43]	20950	1		T3	2		T13	1		T14	1
valid_sources[0x44]	21051	1		T3	2		T13	2		T17	1176
valid_sources[0x45]	21934	1		T13	1		T14	2		T17	485
valid_sources[0x46]	20465	1		T2	1		T13	2		T14	1
valid_sources[0x47]	21450	1		T13	1		T14	1		T17	774
valid_sources[0x48]	21594	1		T12	2		T13	1		T14	1
valid_sources[0x49]	20265	1		T1	16		T3	1		T13	3
valid_sources[0x4a]	20823	1		T2	1		T3	3		T14	2
valid_sources[0x4b]	20620	1		T14	2		T17	651		T26	1
valid_sources[0x4c]	20260	1		T1	31		T17	589		T19	694
valid_sources[0x4d]	23779	1		T9	1		T14	1		T17	980
valid_sources[0x4e]	20904	1		T17	697		T26	5		T19	361
valid_sources[0x4f]	21102	1		T1	2		T3	1		T13	1
valid_sources[0x50]	20905	1		T3	3		T14	1		T17	434
valid_sources[0x51]	21380	1		T13	1		T14	1		T17	284
valid_sources[0x52]	20358	1		T14	2		T17	869		T19	609
valid_sources[0x53]	20373	1		T13	1		T17	297		T26	1
valid_sources[0x54]	21097	1		T2	1		T3	1		T7	1
valid_sources[0x55]	22032	1		T2	1		T25	1		T14	2
valid_sources[0x56]	21322	1		T1	4		T7	1		T9	1
valid_sources[0x57]	21339	1		T2	1		T14	1		T17	1158
valid_sources[0x58]	22099	1		T14	1		T17	1082		T26	3
valid_sources[0x59]	20520	1		T1	13		T3	3		T13	1
valid_sources[0x5a]	21578	1		T13	1		T14	1		T17	1261
valid_sources[0x5b]	20373	1		T14	2		T17	933		T26	3
valid_sources[0x5c]	23512	1		T3	4		T6	2		T13	4
valid_sources[0x5d]	19972	1		T14	1		T17	793		T19	734
valid_sources[0x5e]	21191	1		T12	3		T14	1		T15	1
valid_sources[0x5f]	19737	1		T3	3		T14	1		T17	590
valid_sources[0x60]	19901	1		T1	1		T3	1		T14	1
valid_sources[0x61]	21205	1		T3	7		T14	2		T17	848
valid_sources[0x62]	21919	1		T3	1		T13	3		T14	1
valid_sources[0x63]	19835	1		T1	10		T2	1		T13	1
valid_sources[0x64]	20328	1		T3	1		T14	2		T17	596
valid_sources[0x65]	20812	1		T3	2		T13	2		T14	2
valid_sources[0x66]	21250	1		T13	1		T17	1123		T19	821
valid_sources[0x67]	21412	1		T3	4		T7	1		T9	1
valid_sources[0x68]	21191	1		T2	1		T3	5		T9	1
valid_sources[0x69]	20734	1		T3	2		T13	1		T14	1
valid_sources[0x6a]	21639	1		T3	3		T13	2		T17	1112
valid_sources[0x6b]	21665	1		T14	1		T17	620		T19	1314
valid_sources[0x6c]	20966	1		T14	3		T17	510		T26	1
valid_sources[0x6d]	20770	1		T13	1		T17	723		T26	3
valid_sources[0x6e]	20978	1		T1	6		T14	1		T17	584
valid_sources[0x6f]	21983	1		T1	4		T13	2		T15	2
valid_sources[0x70]	20172	1		T3	8		T12	16		T13	1
valid_sources[0x71]	21755	1		T13	2		T14	2		T17	928
valid_sources[0x72]	21967	1		T3	1		T5	1		T13	4
valid_sources[0x73]	20745	1		T2	1		T3	2		T13	1
valid_sources[0x74]	21367	1		T3	2		T14	1		T17	360
valid_sources[0x75]	20114	1		T13	2		T25	1		T14	1
valid_sources[0x76]	22111	1		T3	2		T14	2		T17	1665
valid_sources[0x77]	20770	1		T3	1		T12	12		T25	1
valid_sources[0x78]	21711	1		T3	1		T7	1		T14	2
valid_sources[0x79]	22047	1		T3	1		T13	1		T17	1305
valid_sources[0x7a]	21328	1		T3	2		T12	1		T13	1
valid_sources[0x7b]	22190	1		T3	2		T13	1		T14	1
valid_sources[0x7c]	21430	1		T1	15		T3	2		T13	1
valid_sources[0x7d]	20515	1		T3	1		T14	2		T17	326
valid_sources[0x7e]	22083	1		T3	7		T13	1		T17	1051
valid_sources[0x7f]	20432	1		T12	25		T14	1		T17	1146
valid_sources[0x80]	22385	1		T3	8		T13	3		T14	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1247586

1

T1

28

T2

1

T3

25

values[0x0]

all_enables

biggest_size

1877032

1

T1

101

T2

9

T3

101

values[0x1]

all_enables

biggest_size

1878871

1

T1

100

T2

6

T3

92