Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	712239854	5900324	0	0
wdog_bark_thold_rd_A	712239854	151816	0	0
wdog_bite_thold_rd_A	712239854	134807	0	0
wdog_ctrl_rd_A	712239854	134817	0	0
wdog_regwen_rd_A	712239854	156644	0	0
wkup_ctrl_rd_A	712239854	134054	0	0
wkup_thold_hi_rd_A	712239854	151494	0	0
wkup_thold_lo_rd_A	712239854	134317	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	712239854	5900324	0	0
T17	102704	215167	0	0
T18	818920	0	0	0
T19	770936	176383	0	0
T20	751045	101154	0	0
T26	543322	0	0	0
T27	17748	0	0	0
T36	0	61943	0	0
T37	0	274879	0	0
T38	0	112032	0	0
T39	0	17119	0	0
T40	0	169187	0	0
T41	0	182948	0	0
T42	0	69923	0	0
T43	217483	0	0	0
T44	339193	0	0	0
T45	306938	0	0	0
T46	61244	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	712239854	151816	0	0
T17	102704	22038	0	0
T18	818920	0	0	0
T19	770936	18396	0	0
T20	751045	10443	0	0
T26	543322	0	0	0
T27	17748	0	0	0
T37	0	26027	0	0
T39	0	1925	0	0
T42	0	3627	0	0
T43	217483	0	0	0
T44	339193	0	0	0
T45	306938	0	0	0
T46	61244	0	0	0
T55	0	6878	0	0
T82	0	18772	0	0
T84	0	15137	0	0
T85	0	5430	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	712239854	134807	0	0
T17	102704	19188	0	0
T18	818920	0	0	0
T19	770936	15842	0	0
T20	751045	9278	0	0
T26	543322	0	0	0
T27	17748	0	0	0
T37	0	23454	0	0
T39	0	1512	0	0
T42	0	3210	0	0
T43	217483	0	0	0
T44	339193	0	0	0
T45	306938	0	0	0
T46	61244	0	0	0
T55	0	6143	0	0
T82	0	16230	0	0
T84	0	14072	0	0
T85	0	4985	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	712239854	134817	0	0
T17	102704	19078	0	0
T18	818920	0	0	0
T19	770936	15953	0	0
T20	751045	9125	0	0
T26	543322	0	0	0
T27	17748	0	0	0
T37	0	23109	0	0
T39	0	1714	0	0
T42	0	3114	0	0
T43	217483	0	0	0
T44	339193	0	0	0
T45	306938	0	0	0
T46	61244	0	0	0
T55	0	5967	0	0
T82	0	16751	0	0
T84	0	13841	0	0
T85	0	4728	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	712239854	156644	0	0
T17	102704	22039	0	0
T18	818920	0	0	0
T19	770936	18967	0	0
T20	751045	10924	0	0
T26	543322	0	0	0
T27	17748	0	0	0
T37	0	26774	0	0
T39	0	2088	0	0
T42	0	3801	0	0
T43	217483	0	0	0
T44	339193	0	0	0
T45	306938	0	0	0
T46	61244	0	0	0
T55	0	7379	0	0
T82	0	18718	0	0
T84	0	15749	0	0
T85	0	5698	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	712239854	134054	0	0
T17	102704	19291	0	0
T18	818920	0	0	0
T19	770936	15636	0	0
T20	751045	8896	0	0
T26	543322	0	0	0
T27	17748	0	0	0
T37	0	22831	0	0
T39	0	1694	0	0
T42	0	3091	0	0
T43	217483	0	0	0
T44	339193	0	0	0
T45	306938	0	0	0
T46	61244	0	0	0
T55	0	6210	0	0
T82	0	16735	0	0
T84	0	13577	0	0
T85	0	4526	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	712239854	151494	0	0
T17	102704	21411	0	0
T18	818920	0	0	0
T19	770936	17688	0	0
T20	751045	10454	0	0
T26	543322	0	0	0
T27	17748	0	0	0
T37	0	25973	0	0
T39	0	1915	0	0
T42	0	3728	0	0
T43	217483	0	0	0
T44	339193	0	0	0
T45	306938	0	0	0
T46	61244	0	0	0
T55	0	7343	0	0
T82	0	18962	0	0
T84	0	15164	0	0
T85	0	5319	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	712239854	134317	0	0
T17	102704	18655	0	0
T18	818920	0	0	0
T19	770936	15405	0	0
T20	751045	9273	0	0
T26	543322	0	0	0
T27	17748	0	0	0
T37	0	22996	0	0
T39	0	1679	0	0
T42	0	2705	0	0
T43	217483	0	0	0
T44	339193	0	0	0
T45	306938	0	0	0
T46	61244	0	0	0
T55	0	6450	0	0
T82	0	17223	0	0
T84	0	13872	0	0
T85	0	4837	0	0