Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	429685	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5253983	1		T1	12		T2	12		T3	12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1396716	1		T1	1		T2	1		T3	1
values[0x0]	2008538	1		T1	9		T2	7		T3	12
values[0x1]	2278414	1		T1	10		T2	11		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	191314	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5492354	1		T1	12		T2	13		T3	14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22690	1		T6	734		T8	2		T9	114
valid_sources[0x01]	21845	1		T5	1		T6	794		T8	1
valid_sources[0x02]	22296	1		T6	281		T8	2		T9	100
valid_sources[0x03]	21200	1		T5	2		T6	248		T9	81
valid_sources[0x04]	21457	1		T5	2		T6	539		T9	82
valid_sources[0x05]	21615	1		T5	2		T6	100		T8	3
valid_sources[0x06]	21693	1		T5	1		T6	424		T8	1
valid_sources[0x07]	22123	1		T5	4		T6	489		T8	1
valid_sources[0x08]	21417	1		T5	3		T6	200		T8	5
valid_sources[0x09]	21833	1		T5	1		T6	148		T8	1
valid_sources[0x0a]	21907	1		T6	7		T9	84		T10	249
valid_sources[0x0b]	21568	1		T5	3		T6	404		T8	2
valid_sources[0x0c]	22098	1		T5	1		T6	521		T8	2
valid_sources[0x0d]	21295	1		T6	442		T8	2		T9	115
valid_sources[0x0e]	21796	1		T5	1		T6	15		T9	86
valid_sources[0x0f]	22934	1		T6	516		T9	88		T10	241
valid_sources[0x10]	22940	1		T5	2		T6	546		T8	2
valid_sources[0x11]	22681	1		T5	1		T6	680		T9	91
valid_sources[0x12]	21717	1		T5	2		T6	675		T8	2
valid_sources[0x13]	22910	1		T6	461		T9	116		T10	258
valid_sources[0x14]	22495	1		T6	642		T9	92		T10	255
valid_sources[0x15]	23440	1		T4	335		T5	1		T6	592
valid_sources[0x16]	21559	1		T6	351		T9	93		T10	282
valid_sources[0x17]	23338	1		T6	715		T8	1		T9	86
valid_sources[0x18]	22904	1		T5	4		T6	446		T8	1
valid_sources[0x19]	21817	1		T6	453		T8	3		T9	103
valid_sources[0x1a]	23338	1		T6	311		T9	88		T10	236
valid_sources[0x1b]	21596	1		T5	2		T6	389		T9	116
valid_sources[0x1c]	21316	1		T3	1		T5	4		T6	371
valid_sources[0x1d]	22742	1		T5	1		T6	689		T9	108
valid_sources[0x1e]	22619	1		T5	2		T6	631		T8	2
valid_sources[0x1f]	23160	1		T6	690		T7	4		T9	91
valid_sources[0x20]	22609	1		T5	1		T6	592		T8	1
valid_sources[0x21]	22954	1		T5	3		T6	627		T8	2
valid_sources[0x22]	21606	1		T5	2		T6	133		T8	5
valid_sources[0x23]	21350	1		T5	3		T6	996		T9	120
valid_sources[0x24]	22880	1		T5	1		T6	843		T9	100
valid_sources[0x25]	22500	1		T6	556		T8	4		T9	106
valid_sources[0x26]	22305	1		T5	1		T6	710		T8	1
valid_sources[0x27]	21806	1		T5	1		T6	554		T9	93
valid_sources[0x28]	21014	1		T6	481		T8	2		T9	99
valid_sources[0x29]	22811	1		T5	2		T6	244		T8	1
valid_sources[0x2a]	21307	1		T5	2		T6	266		T9	83
valid_sources[0x2b]	21857	1		T6	346		T8	1		T9	106
valid_sources[0x2c]	20727	1		T6	275		T9	69		T10	228
valid_sources[0x2d]	23138	1		T6	744		T9	96		T10	275
valid_sources[0x2e]	21970	1		T6	370		T9	98		T10	236
valid_sources[0x2f]	22171	1		T6	418		T9	91		T10	232
valid_sources[0x30]	22257	1		T5	4		T6	101		T9	85
valid_sources[0x31]	22531	1		T6	322		T9	113		T10	278
valid_sources[0x32]	21372	1		T5	3		T6	657		T8	2
valid_sources[0x33]	20985	1		T5	1		T6	12		T8	2
valid_sources[0x34]	21898	1		T5	2		T6	9		T8	2
valid_sources[0x35]	21627	1		T6	719		T9	100		T10	295
valid_sources[0x36]	22053	1		T5	4		T6	60		T8	1
valid_sources[0x37]	20858	1		T6	200		T9	83		T10	264
valid_sources[0x38]	22672	1		T6	630		T8	1		T9	102
valid_sources[0x39]	21690	1		T5	2		T6	453		T8	1
valid_sources[0x3a]	21174	1		T5	1		T6	384		T9	76
valid_sources[0x3b]	22711	1		T5	3		T6	397		T8	1
valid_sources[0x3c]	22110	1		T6	411		T9	78		T10	271
valid_sources[0x3d]	22507	1		T6	322		T8	1		T9	89
valid_sources[0x3e]	22530	1		T5	2		T6	998		T7	1
valid_sources[0x3f]	22643	1		T6	1074		T9	96		T10	265
valid_sources[0x40]	22934	1		T6	1219		T9	110		T10	253
valid_sources[0x41]	22015	1		T5	2		T6	402		T8	1
valid_sources[0x42]	21421	1		T6	460		T9	97		T10	239
valid_sources[0x43]	23242	1		T5	2		T6	502		T8	3
valid_sources[0x44]	20966	1		T1	1		T5	1		T6	454
valid_sources[0x45]	21250	1		T6	464		T7	4		T8	1
valid_sources[0x46]	23722	1		T5	2		T6	248		T8	3
valid_sources[0x47]	22872	1		T5	1		T6	394		T9	92
valid_sources[0x48]	22420	1		T6	344		T9	104		T10	263
valid_sources[0x49]	20264	1		T5	1		T6	358		T9	91
valid_sources[0x4a]	22523	1		T6	900		T8	3		T9	87
valid_sources[0x4b]	21138	1		T5	2		T6	470		T8	3
valid_sources[0x4c]	22804	1		T5	6		T6	215		T8	2
valid_sources[0x4d]	22415	1		T5	3		T6	685		T8	4
valid_sources[0x4e]	23055	1		T5	1		T6	667		T9	114
valid_sources[0x4f]	21904	1		T5	1		T6	649		T9	119
valid_sources[0x50]	22697	1		T3	6		T5	1		T6	890
valid_sources[0x51]	21073	1		T6	172		T9	105		T10	267
valid_sources[0x52]	23140	1		T5	2		T6	444		T9	88
valid_sources[0x53]	21691	1		T5	3		T6	7		T8	1
valid_sources[0x54]	22015	1		T6	553		T9	96		T10	231
valid_sources[0x55]	21297	1		T3	3		T5	1		T6	123
valid_sources[0x56]	21720	1		T5	3		T6	564		T9	123
valid_sources[0x57]	22021	1		T5	1		T6	446		T8	2
valid_sources[0x58]	22747	1		T5	3		T6	503		T9	93
valid_sources[0x59]	23196	1		T5	1		T6	877		T8	1
valid_sources[0x5a]	23665	1		T5	1		T6	269		T9	100
valid_sources[0x5b]	21570	1		T5	3		T6	222		T9	95
valid_sources[0x5c]	21568	1		T5	1		T6	261		T8	1
valid_sources[0x5d]	22763	1		T5	5		T6	385		T9	95
valid_sources[0x5e]	21722	1		T6	261		T8	1		T9	95
valid_sources[0x5f]	22375	1		T5	3		T6	312		T8	1
valid_sources[0x60]	20773	1		T6	169		T8	3		T9	84
valid_sources[0x61]	22692	1		T6	849		T9	79		T10	228
valid_sources[0x62]	21990	1		T6	217		T8	1		T9	89
valid_sources[0x63]	20766	1		T5	4		T6	186		T9	81
valid_sources[0x64]	22344	1		T5	1		T6	584		T9	90
valid_sources[0x65]	22416	1		T5	3		T6	203		T8	2
valid_sources[0x66]	22353	1		T6	11		T9	90		T10	246
valid_sources[0x67]	22188	1		T9	88		T10	257		T11	515
valid_sources[0x68]	24452	1		T6	156		T8	5		T9	86
valid_sources[0x69]	21351	1		T5	2		T6	714		T8	3
valid_sources[0x6a]	21933	1		T5	1		T6	541		T9	81
valid_sources[0x6b]	21952	1		T5	4		T6	122		T9	85
valid_sources[0x6c]	22169	1		T5	1		T6	537		T9	94
valid_sources[0x6d]	23111	1		T5	2		T6	1434		T9	114
valid_sources[0x6e]	21742	1		T5	2		T6	647		T8	2
valid_sources[0x6f]	23199	1		T5	2		T6	804		T8	1
valid_sources[0x70]	24244	1		T5	1		T6	661		T9	99
valid_sources[0x71]	21900	1		T6	645		T9	90		T10	251
valid_sources[0x72]	22281	1		T6	600		T8	1		T9	99
valid_sources[0x73]	22417	1		T6	1026		T9	96		T10	251
valid_sources[0x74]	21649	1		T5	1		T6	294		T9	99
valid_sources[0x75]	22831	1		T5	2		T6	431		T9	96
valid_sources[0x76]	21949	1		T5	2		T6	36		T9	107
valid_sources[0x77]	23011	1		T5	3		T6	876		T8	4
valid_sources[0x78]	23219	1		T5	1		T6	1169		T9	90
valid_sources[0x79]	25397	1		T5	1		T6	795		T9	83
valid_sources[0x7a]	21629	1		T6	630		T8	1		T9	105
valid_sources[0x7b]	22026	1		T6	850		T9	94		T10	222
valid_sources[0x7c]	21469	1		T2	19		T6	78		T8	1
valid_sources[0x7d]	22424	1		T5	1		T6	550		T7	4
valid_sources[0x7e]	21143	1		T3	2		T5	1		T6	20
valid_sources[0x7f]	21819	1		T6	124		T8	1		T9	105
valid_sources[0x80]	21447	1		T6	728		T9	103		T10	245

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1309984

1

T4

14

T5

19

T6

27801

values[0x0]

all_enables

biggest_size

1973072

1

T1

7

T2

4

T3

9

values[0x1]

all_enables

biggest_size

1970927

1

T1

5

T2

8

T3

3