Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	717270971	6277114	0	0
wdog_bark_thold_rd_A	717270971	102660	0	0
wdog_bite_thold_rd_A	717270971	89302	0	0
wdog_ctrl_rd_A	717270971	89692	0	0
wdog_regwen_rd_A	717270971	102795	0	0
wkup_ctrl_rd_A	717270971	88533	0	0
wkup_thold_hi_rd_A	717270971	102728	0	0
wkup_thold_lo_rd_A	717270971	91269	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717270971	6277114	0	0
T6	531293	136826	0	0
T7	143255	0	0	0
T8	207968	0	0	0
T9	120028	24184	0	0
T10	303583	68690	0	0
T11	548775	147928	0	0
T25	129378	300849	0	0
T26	12248	0	0	0
T27	0	228841	0	0
T29	0	151000	0	0
T30	134767	0	0	0
T31	215295	0	0	0
T38	0	257200	0	0
T39	0	44231	0	0
T40	0	289327	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717270971	102660	0	0
T9	120028	2424	0	0
T10	303583	6936	0	0
T11	548775	0	0	0
T25	129378	30543	0	0
T26	12248	0	0	0
T27	830617	0	0	0
T28	225063	0	0	0
T30	134767	0	0	0
T31	215295	0	0	0
T87	0	12059	0	0
T88	0	6798	0	0
T89	0	3019	0	0
T90	0	12453	0	0
T91	0	2887	0	0
T92	0	5359	0	0
T93	0	7301	0	0
T94	400966	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717270971	89302	0	0
T9	120028	2319	0	0
T10	303583	6265	0	0
T11	548775	0	0	0
T25	129378	26466	0	0
T26	12248	0	0	0
T27	830617	0	0	0
T28	225063	0	0	0
T30	134767	0	0	0
T31	215295	0	0	0
T87	0	10423	0	0
T88	0	6065	0	0
T89	0	2523	0	0
T90	0	10513	0	0
T91	0	2525	0	0
T92	0	4671	0	0
T93	0	6201	0	0
T94	400966	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717270971	89692	0	0
T9	120028	2058	0	0
T10	303583	6199	0	0
T11	548775	0	0	0
T25	129378	26224	0	0
T26	12248	0	0	0
T27	830617	0	0	0
T28	225063	0	0	0
T30	134767	0	0	0
T31	215295	0	0	0
T87	0	10539	0	0
T88	0	5685	0	0
T89	0	2564	0	0
T90	0	10637	0	0
T91	0	2714	0	0
T92	0	5152	0	0
T93	0	6445	0	0
T94	400966	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717270971	102795	0	0
T9	120028	2304	0	0
T10	303583	6747	0	0
T11	548775	0	0	0
T25	129378	30509	0	0
T26	12248	0	0	0
T27	830617	0	0	0
T28	225063	0	0	0
T30	134767	0	0	0
T31	215295	0	0	0
T87	0	12345	0	0
T88	0	6818	0	0
T89	0	2868	0	0
T90	0	12639	0	0
T91	0	2748	0	0
T92	0	5606	0	0
T93	0	7366	0	0
T94	400966	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717270971	88533	0	0
T9	120028	2018	0	0
T10	303583	5803	0	0
T11	548775	0	0	0
T25	129378	26512	0	0
T26	12248	0	0	0
T27	830617	0	0	0
T28	225063	0	0	0
T30	134767	0	0	0
T31	215295	0	0	0
T87	0	10300	0	0
T88	0	5364	0	0
T89	0	2565	0	0
T90	0	10690	0	0
T91	0	2640	0	0
T92	0	4770	0	0
T93	0	6386	0	0
T94	400966	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717270971	102728	0	0
T9	120028	2363	0	0
T10	303583	6885	0	0
T11	548775	0	0	0
T25	129378	30475	0	0
T26	12248	0	0	0
T27	830617	0	0	0
T28	225063	0	0	0
T30	134767	0	0	0
T31	215295	0	0	0
T87	0	12156	0	0
T88	0	6501	0	0
T89	0	3348	0	0
T90	0	12474	0	0
T91	0	3068	0	0
T92	0	5528	0	0
T93	0	7097	0	0
T94	400966	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	717270971	91269	0	0
T9	120028	2072	0	0
T10	303583	6085	0	0
T11	548775	0	0	0
T25	129378	26889	0	0
T26	12248	0	0	0
T27	830617	0	0	0
T28	225063	0	0	0
T30	134767	0	0	0
T31	215295	0	0	0
T87	0	10736	0	0
T88	0	5736	0	0
T89	0	2845	0	0
T90	0	11103	0	0
T91	0	2635	0	0
T92	0	5104	0	0
T93	0	6483	0	0
T94	400966	0	0	0