Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	383283	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4765553	1		T1	17		T2	169		T3	12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1265161	1		T1	1		T2	56		T3	1
values[0x0]	1820603	1		T1	8		T2	110		T3	11
values[0x1]	2063072	1		T1	13		T2	119		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	170262	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4978574	1		T1	19		T2	183		T3	12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21567	1		T1	1		T2	2		T10	60
valid_sources[0x01]	22090	1		T2	1		T3	1		T10	344
valid_sources[0x02]	20400	1		T2	5		T10	197		T15	2
valid_sources[0x03]	18613	1		T2	1		T10	353		T16	2
valid_sources[0x04]	18476	1		T2	2		T10	512		T15	1
valid_sources[0x05]	20528	1		T2	2		T3	1		T10	336
valid_sources[0x06]	17625	1		T10	258		T13	1		T15	1
valid_sources[0x07]	21675	1		T1	1		T2	2		T10	604
valid_sources[0x08]	20521	1		T2	1		T10	265		T15	3
valid_sources[0x09]	19316	1		T10	121		T12	1		T15	1
valid_sources[0x0a]	19123	1		T2	1		T10	157		T17	38
valid_sources[0x0b]	20363	1		T2	2		T10	274		T15	1
valid_sources[0x0c]	18282	1		T2	1		T7	1		T10	311
valid_sources[0x0d]	21249	1		T2	1		T10	515		T15	2
valid_sources[0x0e]	20929	1		T10	710		T15	1		T17	54
valid_sources[0x0f]	19424	1		T10	481		T15	4		T17	38
valid_sources[0x10]	21167	1		T5	1		T10	97		T17	43
valid_sources[0x11]	18511	1		T2	2		T10	220		T16	1
valid_sources[0x12]	18876	1		T2	1		T10	729		T17	42
valid_sources[0x13]	19608	1		T8	22		T10	276		T15	2
valid_sources[0x14]	20439	1		T2	2		T10	490		T15	1
valid_sources[0x15]	20282	1		T10	459		T15	3		T17	39
valid_sources[0x16]	18989	1		T2	1		T10	272		T12	1
valid_sources[0x17]	18863	1		T2	2		T10	391		T17	51
valid_sources[0x18]	20975	1		T2	1		T10	596		T15	1
valid_sources[0x19]	20261	1		T1	1		T2	1		T10	262
valid_sources[0x1a]	21156	1		T2	1		T10	45		T13	1
valid_sources[0x1b]	21505	1		T2	1		T10	68		T17	38
valid_sources[0x1c]	19677	1		T2	2		T10	183		T15	1
valid_sources[0x1d]	19772	1		T10	136		T17	49		T18	1263
valid_sources[0x1e]	19704	1		T2	3		T10	568		T17	44
valid_sources[0x1f]	19570	1		T2	1		T10	599		T15	1
valid_sources[0x20]	22189	1		T10	287		T15	1		T17	55
valid_sources[0x21]	20065	1		T2	3		T10	433		T15	2
valid_sources[0x22]	20300	1		T2	1		T10	609		T12	1
valid_sources[0x23]	19705	1		T1	1		T2	1		T5	1
valid_sources[0x24]	20647	1		T2	1		T10	597		T17	42
valid_sources[0x25]	20713	1		T1	1		T2	1		T10	396
valid_sources[0x26]	21121	1		T2	2		T10	367		T15	2
valid_sources[0x27]	20155	1		T2	3		T10	53		T12	1
valid_sources[0x28]	21354	1		T2	2		T10	366		T13	1
valid_sources[0x29]	19892	1		T2	1		T10	458		T15	3
valid_sources[0x2a]	19922	1		T2	2		T10	61		T15	1
valid_sources[0x2b]	20684	1		T10	112		T11	3		T15	1
valid_sources[0x2c]	19556	1		T10	244		T15	1		T17	34
valid_sources[0x2d]	21386	1		T2	2		T10	372		T15	2
valid_sources[0x2e]	19891	1		T2	1		T10	477		T17	53
valid_sources[0x2f]	19580	1		T1	1		T10	239		T12	1
valid_sources[0x30]	18920	1		T1	1		T2	1		T7	2
valid_sources[0x31]	21136	1		T10	341		T15	2		T17	34
valid_sources[0x32]	19375	1		T10	745		T15	4		T17	46
valid_sources[0x33]	20749	1		T10	204		T15	1		T17	49
valid_sources[0x34]	20324	1		T2	1		T9	20		T10	548
valid_sources[0x35]	20113	1		T2	1		T10	116		T17	38
valid_sources[0x36]	20524	1		T2	1		T10	14		T15	3
valid_sources[0x37]	19669	1		T2	3		T10	84		T17	44
valid_sources[0x38]	18805	1		T2	1		T10	241		T17	50
valid_sources[0x39]	19059	1		T10	161		T15	3		T17	50
valid_sources[0x3a]	18391	1		T2	1		T10	248		T15	1
valid_sources[0x3b]	21121	1		T2	3		T5	1		T7	1
valid_sources[0x3c]	21365	1		T5	1		T10	96		T15	3
valid_sources[0x3d]	18321	1		T2	1		T10	161		T16	2
valid_sources[0x3e]	18728	1		T2	1		T10	435		T15	2
valid_sources[0x3f]	20207	1		T5	1		T7	1		T10	193
valid_sources[0x40]	17893	1		T2	2		T10	361		T15	2
valid_sources[0x41]	18802	1		T2	1		T10	272		T17	55
valid_sources[0x42]	18361	1		T10	263		T17	55		T18	1182
valid_sources[0x43]	19344	1		T2	1		T10	334		T15	1
valid_sources[0x44]	19931	1		T2	1		T10	696		T15	2
valid_sources[0x45]	21328	1		T2	2		T10	332		T15	2
valid_sources[0x46]	20313	1		T10	128		T15	2		T17	50
valid_sources[0x47]	19964	1		T2	2		T3	1		T10	305
valid_sources[0x48]	20585	1		T2	1		T10	384		T17	40
valid_sources[0x49]	20747	1		T2	1		T10	45		T13	1
valid_sources[0x4a]	20322	1		T10	397		T15	2		T17	48
valid_sources[0x4b]	19582	1		T2	2		T10	792		T13	1
valid_sources[0x4c]	19518	1		T10	603		T15	2		T17	49
valid_sources[0x4d]	20315	1		T10	335		T12	1		T17	50
valid_sources[0x4e]	20059	1		T2	1		T10	848		T15	1
valid_sources[0x4f]	19983	1		T10	103		T17	33		T38	3
valid_sources[0x50]	19274	1		T10	267		T15	4		T17	35
valid_sources[0x51]	19912	1		T10	34		T15	1		T17	48
valid_sources[0x52]	21004	1		T1	1		T2	2		T10	150
valid_sources[0x53]	21206	1		T2	3		T10	186		T15	1
valid_sources[0x54]	21816	1		T7	1		T10	193		T17	44
valid_sources[0x55]	20034	1		T10	190		T17	39		T18	1210
valid_sources[0x56]	20138	1		T2	1		T10	171		T15	1
valid_sources[0x57]	20418	1		T10	614		T17	42		T104	1
valid_sources[0x58]	20051	1		T2	2		T10	168		T11	1
valid_sources[0x59]	19059	1		T1	1		T10	42		T15	2
valid_sources[0x5a]	19442	1		T2	3		T5	1		T10	172
valid_sources[0x5b]	19943	1		T2	2		T10	528		T15	2
valid_sources[0x5c]	20784	1		T2	1		T10	409		T17	42
valid_sources[0x5d]	17787	1		T2	2		T10	361		T13	1
valid_sources[0x5e]	17959	1		T2	3		T3	1		T10	150
valid_sources[0x5f]	21559	1		T10	146		T17	51		T18	1183
valid_sources[0x60]	20034	1		T3	2		T10	118		T17	46
valid_sources[0x61]	20283	1		T10	747		T15	1		T17	27
valid_sources[0x62]	18844	1		T2	2		T10	261		T17	49
valid_sources[0x63]	18789	1		T2	1		T10	226		T13	1
valid_sources[0x64]	20331	1		T2	2		T10	321		T15	2
valid_sources[0x65]	21883	1		T10	157		T15	1		T17	46
valid_sources[0x66]	19762	1		T2	1		T7	2		T10	196
valid_sources[0x67]	21916	1		T2	1		T10	223		T14	22
valid_sources[0x68]	20952	1		T10	155		T15	2		T17	49
valid_sources[0x69]	18851	1		T10	96		T17	52		T119	1
valid_sources[0x6a]	19632	1		T2	1		T10	338		T17	41
valid_sources[0x6b]	20121	1		T2	1		T10	167		T17	56
valid_sources[0x6c]	20586	1		T10	173		T17	55		T34	1
valid_sources[0x6d]	19622	1		T2	1		T10	30		T15	2
valid_sources[0x6e]	19961	1		T3	1		T10	258		T17	33
valid_sources[0x6f]	20062	1		T2	1		T10	106		T15	4
valid_sources[0x70]	21350	1		T2	4		T10	342		T17	47
valid_sources[0x71]	19940	1		T2	1		T10	577		T17	41
valid_sources[0x72]	19934	1		T10	246		T17	70		T34	1
valid_sources[0x73]	20577	1		T10	364		T15	2		T17	38
valid_sources[0x74]	19253	1		T2	1		T10	484		T15	1
valid_sources[0x75]	20134	1		T2	1		T10	197		T17	53
valid_sources[0x76]	20104	1		T1	1		T2	1		T10	386
valid_sources[0x77]	19334	1		T2	1		T10	233		T13	1
valid_sources[0x78]	21092	1		T10	425		T15	1		T17	47
valid_sources[0x79]	22437	1		T2	1		T7	1		T10	322
valid_sources[0x7a]	20109	1		T2	2		T10	192		T17	51
valid_sources[0x7b]	19901	1		T2	3		T10	406		T15	2
valid_sources[0x7c]	19147	1		T2	2		T10	208		T12	1
valid_sources[0x7d]	22248	1		T10	337		T15	1		T17	57
valid_sources[0x7e]	20239	1		T2	1		T5	1		T10	132
valid_sources[0x7f]	20434	1		T2	1		T5	1		T10	364
valid_sources[0x80]	20308	1		T10	815		T15	3		T17	43

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1187737

1

T2

25

T4

1

T6

1

values[0x0]

all_enables

biggest_size

1788641

1

T1

7

T2

70

T3

8

values[0x1]

all_enables

biggest_size

1789175

1

T1

10

T2

74

T3

4