Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	667083697	5614086	0	0
wdog_bark_thold_rd_A	667083697	139061	0	0
wdog_bite_thold_rd_A	667083697	121193	0	0
wdog_ctrl_rd_A	667083697	122028	0	0
wdog_regwen_rd_A	667083697	141130	0	0
wkup_ctrl_rd_A	667083697	122208	0	0
wkup_thold_hi_rd_A	667083697	138064	0	0
wkup_thold_lo_rd_A	667083697	122359	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667083697	5614086	0	0
T10	386004	81500	0	0
T11	421207	0	0	0
T12	8995	0	0	0
T13	30137	0	0	0
T14	42813	0	0	0
T15	159250	0	0	0
T16	181892	0	0	0
T17	529222	12636	0	0
T18	0	355218	0	0
T22	123159	0	0	0
T34	6325	0	0	0
T39	0	404889	0	0
T41	0	72152	0	0
T46	0	58865	0	0
T47	0	97457	0	0
T48	0	265124	0	0
T49	0	236123	0	0
T50	0	80862	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667083697	139061	0	0
T10	386004	7911	0	0
T11	421207	0	0	0
T12	8995	0	0	0
T13	30137	0	0	0
T14	42813	0	0	0
T15	159250	0	0	0
T16	181892	0	0	0
T17	529222	0	0	0
T18	0	37215	0	0
T22	123159	0	0	0
T33	0	12112	0	0
T34	6325	0	0	0
T41	0	4008	0	0
T46	0	3198	0	0
T55	0	2539	0	0
T56	0	8702	0	0
T76	0	17265	0	0
T100	0	1467	0	0
T101	0	9714	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667083697	121193	0	0
T10	386004	6864	0	0
T11	421207	0	0	0
T12	8995	0	0	0
T13	30137	0	0	0
T14	42813	0	0	0
T15	159250	0	0	0
T16	181892	0	0	0
T17	529222	0	0	0
T18	0	32268	0	0
T22	123159	0	0	0
T33	0	10863	0	0
T34	6325	0	0	0
T41	0	3242	0	0
T46	0	2838	0	0
T55	0	2369	0	0
T56	0	7556	0	0
T76	0	14897	0	0
T100	0	1341	0	0
T101	0	8776	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667083697	122028	0	0
T10	386004	6974	0	0
T11	421207	0	0	0
T12	8995	0	0	0
T13	30137	0	0	0
T14	42813	0	0	0
T15	159250	0	0	0
T16	181892	0	0	0
T17	529222	0	0	0
T18	0	32153	0	0
T22	123159	0	0	0
T33	0	11477	0	0
T34	6325	0	0	0
T41	0	3183	0	0
T46	0	2841	0	0
T55	0	2398	0	0
T56	0	7757	0	0
T76	0	15155	0	0
T100	0	1263	0	0
T101	0	8648	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667083697	141130	0	0
T10	386004	8064	0	0
T11	421207	0	0	0
T12	8995	0	0	0
T13	30137	0	0	0
T14	42813	0	0	0
T15	159250	0	0	0
T16	181892	0	0	0
T17	529222	0	0	0
T18	0	36966	0	0
T22	123159	0	0	0
T33	0	12897	0	0
T34	6325	0	0	0
T41	0	4057	0	0
T46	0	3486	0	0
T55	0	2631	0	0
T56	0	8942	0	0
T76	0	17675	0	0
T100	0	1396	0	0
T101	0	10010	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667083697	122208	0	0
T10	386004	7127	0	0
T11	421207	0	0	0
T12	8995	0	0	0
T13	30137	0	0	0
T14	42813	0	0	0
T15	159250	0	0	0
T16	181892	0	0	0
T17	529222	0	0	0
T18	0	31682	0	0
T22	123159	0	0	0
T33	0	11103	0	0
T34	6325	0	0	0
T41	0	3329	0	0
T46	0	2476	0	0
T55	0	2382	0	0
T56	0	8102	0	0
T76	0	15700	0	0
T100	0	1167	0	0
T101	0	8562	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667083697	138064	0	0
T10	386004	8156	0	0
T11	421207	0	0	0
T12	8995	0	0	0
T13	30137	0	0	0
T14	42813	0	0	0
T15	159250	0	0	0
T16	181892	0	0	0
T17	529222	0	0	0
T18	0	36009	0	0
T22	123159	0	0	0
T33	0	12120	0	0
T34	6325	0	0	0
T41	0	3938	0	0
T46	0	3138	0	0
T55	0	2892	0	0
T56	0	8812	0	0
T76	0	16817	0	0
T100	0	1317	0	0
T101	0	10267	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667083697	122359	0	0
T10	386004	6678	0	0
T11	421207	0	0	0
T12	8995	0	0	0
T13	30137	0	0	0
T14	42813	0	0	0
T15	159250	0	0	0
T16	181892	0	0	0
T17	529222	0	0	0
T18	0	32526	0	0
T22	123159	0	0	0
T33	0	11535	0	0
T34	6325	0	0	0
T41	0	3051	0	0
T46	0	2833	0	0
T55	0	2436	0	0
T56	0	8018	0	0
T76	0	15105	0	0
T100	0	1269	0	0
T101	0	8603	0	0