Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	347332	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4236017	1		T1	13		T2	11		T3	12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1127027	1		T1	1		T2	1		T3	1
values[0x0]	1618068	1		T1	10		T2	12		T3	7
values[0x1]	1838254	1		T1	9		T2	6		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154722	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4428627	1		T1	13		T2	11		T3	12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17389	1		T12	309		T15	543		T39	1
valid_sources[0x01]	16947	1		T13	2		T14	1		T15	512
valid_sources[0x02]	17622	1		T7	1		T14	3		T15	573
valid_sources[0x03]	17780	1		T7	2		T13	1		T14	2
valid_sources[0x04]	17270	1		T7	4		T14	1		T15	474
valid_sources[0x05]	17097	1		T7	1		T13	2		T15	555
valid_sources[0x06]	17808	1		T7	3		T13	1		T14	1
valid_sources[0x07]	18299	1		T13	1		T15	615		T37	2
valid_sources[0x08]	18058	1		T5	1		T7	2		T13	2
valid_sources[0x09]	17295	1		T13	1		T14	2		T15	557
valid_sources[0x0a]	17913	1		T7	4		T13	1		T14	1
valid_sources[0x0b]	17944	1		T15	561		T37	1		T42	1
valid_sources[0x0c]	17247	1		T14	3		T15	522		T39	2
valid_sources[0x0d]	18257	1		T13	4		T15	491		T37	1
valid_sources[0x0e]	18213	1		T15	487		T37	4		T39	3
valid_sources[0x0f]	16929	1		T7	1		T13	1		T15	528
valid_sources[0x10]	18164	1		T14	1		T15	477		T37	2
valid_sources[0x11]	17052	1		T13	4		T14	2		T15	588
valid_sources[0x12]	18105	1		T7	3		T14	3		T15	530
valid_sources[0x13]	17486	1		T7	5		T15	524		T37	2
valid_sources[0x14]	17474	1		T13	2		T14	1		T15	571
valid_sources[0x15]	18890	1		T13	1		T15	560		T37	4
valid_sources[0x16]	18069	1		T7	1		T13	3		T14	3
valid_sources[0x17]	17510	1		T15	598		T37	1		T42	2
valid_sources[0x18]	17753	1		T7	3		T15	506		T39	2
valid_sources[0x19]	18367	1		T13	2		T15	516		T37	1
valid_sources[0x1a]	18355	1		T5	1		T13	1		T15	623
valid_sources[0x1b]	17588	1		T14	1		T15	545		T37	2
valid_sources[0x1c]	17648	1		T13	4		T15	551		T39	3
valid_sources[0x1d]	19016	1		T5	1		T6	1		T14	1
valid_sources[0x1e]	17652	1		T3	2		T7	3		T15	496
valid_sources[0x1f]	17247	1		T13	1		T14	2		T15	568
valid_sources[0x20]	16954	1		T7	3		T15	532		T37	2
valid_sources[0x21]	18408	1		T1	1		T5	1		T7	2
valid_sources[0x22]	18712	1		T13	1		T14	1		T15	545
valid_sources[0x23]	17582	1		T7	3		T13	1		T14	1
valid_sources[0x24]	16749	1		T5	1		T7	2		T13	3
valid_sources[0x25]	17386	1		T7	1		T13	1		T14	4
valid_sources[0x26]	17498	1		T7	1		T14	1		T15	502
valid_sources[0x27]	17904	1		T13	3		T14	2		T15	520
valid_sources[0x28]	18035	1		T5	1		T7	1		T13	1
valid_sources[0x29]	18861	1		T7	7		T13	1		T14	2
valid_sources[0x2a]	19391	1		T14	2		T15	515		T39	2
valid_sources[0x2b]	18094	1		T7	2		T13	1		T15	534
valid_sources[0x2c]	16943	1		T13	3		T14	3		T15	553
valid_sources[0x2d]	17716	1		T13	4		T14	2		T15	508
valid_sources[0x2e]	17630	1		T14	1		T15	521		T37	2
valid_sources[0x2f]	19053	1		T6	1		T7	1		T10	294
valid_sources[0x30]	17620	1		T15	570		T37	1		T39	2
valid_sources[0x31]	17564	1		T7	3		T13	1		T14	1
valid_sources[0x32]	18399	1		T13	3		T15	556		T39	5
valid_sources[0x33]	18243	1		T13	1		T14	4		T15	541
valid_sources[0x34]	17912	1		T2	19		T7	1		T15	496
valid_sources[0x35]	17279	1		T13	1		T14	1		T15	498
valid_sources[0x36]	18229	1		T7	2		T13	1		T14	1
valid_sources[0x37]	18966	1		T13	1		T15	478		T39	1
valid_sources[0x38]	17551	1		T13	2		T14	2		T15	494
valid_sources[0x39]	20487	1		T13	1		T15	527		T39	1
valid_sources[0x3a]	17562	1		T7	4		T13	5		T15	552
valid_sources[0x3b]	17322	1		T13	1		T14	1		T15	514
valid_sources[0x3c]	18307	1		T7	1		T13	2		T15	522
valid_sources[0x3d]	17846	1		T1	1		T13	2		T14	4
valid_sources[0x3e]	18306	1		T7	1		T8	5		T13	2
valid_sources[0x3f]	16456	1		T7	1		T13	1		T14	1
valid_sources[0x40]	17849	1		T15	605		T37	2		T39	5
valid_sources[0x41]	18074	1		T13	5		T14	3		T15	530
valid_sources[0x42]	18157	1		T14	2		T15	471		T37	1
valid_sources[0x43]	17443	1		T13	1		T14	1		T15	583
valid_sources[0x44]	19260	1		T7	3		T13	1		T14	2
valid_sources[0x45]	18581	1		T15	506		T37	4		T39	2
valid_sources[0x46]	18140	1		T13	2		T14	1		T15	433
valid_sources[0x47]	18092	1		T5	1		T6	1		T7	3
valid_sources[0x48]	16321	1		T14	1		T15	571		T39	1
valid_sources[0x49]	19539	1		T14	1		T15	584		T16	1076
valid_sources[0x4a]	18288	1		T6	1		T7	1		T13	3
valid_sources[0x4b]	19913	1		T13	1		T14	1		T15	538
valid_sources[0x4c]	16894	1		T5	1		T13	1		T14	5
valid_sources[0x4d]	17900	1		T6	2		T7	1		T13	1
valid_sources[0x4e]	18056	1		T1	1		T13	2		T14	1
valid_sources[0x4f]	17534	1		T7	1		T13	2		T14	2
valid_sources[0x50]	17236	1		T7	4		T13	1		T14	3
valid_sources[0x51]	17719	1		T13	2		T15	536		T39	6
valid_sources[0x52]	18197	1		T13	5		T14	5		T15	558
valid_sources[0x53]	17553	1		T14	2		T15	523		T37	3
valid_sources[0x54]	17923	1		T7	4		T14	1		T15	541
valid_sources[0x55]	17192	1		T13	3		T14	4		T15	534
valid_sources[0x56]	17964	1		T7	1		T13	1		T14	1
valid_sources[0x57]	17477	1		T13	1		T14	3		T15	575
valid_sources[0x58]	17397	1		T13	1		T14	4		T15	515
valid_sources[0x59]	17465	1		T7	4		T14	2		T15	481
valid_sources[0x5a]	19608	1		T7	3		T13	1		T14	2
valid_sources[0x5b]	16945	1		T7	3		T15	555		T39	2
valid_sources[0x5c]	17625	1		T13	1		T15	502		T37	3
valid_sources[0x5d]	16915	1		T6	1		T7	1		T14	1
valid_sources[0x5e]	18095	1		T13	4		T14	4		T15	601
valid_sources[0x5f]	17600	1		T3	1		T14	1		T15	500
valid_sources[0x60]	18624	1		T7	1		T14	2		T15	510
valid_sources[0x61]	17481	1		T1	4		T14	3		T15	522
valid_sources[0x62]	18669	1		T13	3		T15	570		T37	3
valid_sources[0x63]	17730	1		T13	1		T14	1		T22	16
valid_sources[0x64]	17266	1		T5	2		T7	3		T13	2
valid_sources[0x65]	18365	1		T7	2		T13	6		T15	568
valid_sources[0x66]	17472	1		T13	4		T14	4		T15	470
valid_sources[0x67]	17270	1		T13	1		T14	3		T15	530
valid_sources[0x68]	18492	1		T3	1		T7	1		T13	1
valid_sources[0x69]	19646	1		T13	1		T14	3		T15	573
valid_sources[0x6a]	18045	1		T13	4		T15	511		T37	3
valid_sources[0x6b]	18375	1		T7	5		T14	3		T15	517
valid_sources[0x6c]	17361	1		T14	1		T15	470		T39	2
valid_sources[0x6d]	18232	1		T7	1		T13	1		T14	2
valid_sources[0x6e]	19660	1		T3	1		T15	545		T37	1
valid_sources[0x6f]	17338	1		T13	3		T14	1		T15	526
valid_sources[0x70]	17651	1		T14	1		T15	586		T37	1
valid_sources[0x71]	17945	1		T7	2		T14	2		T15	469
valid_sources[0x72]	18223	1		T13	2		T14	2		T15	511
valid_sources[0x73]	17334	1		T7	2		T13	1		T14	2
valid_sources[0x74]	17573	1		T7	11		T13	2		T14	2
valid_sources[0x75]	17891	1		T1	2		T7	1		T14	4
valid_sources[0x76]	18147	1		T5	1		T13	1		T14	1
valid_sources[0x77]	17491	1		T13	1		T15	489		T37	2
valid_sources[0x78]	18129	1		T6	1		T7	5		T13	3
valid_sources[0x79]	16676	1		T7	4		T13	2		T14	1
valid_sources[0x7a]	18190	1		T13	4		T14	1		T15	455
valid_sources[0x7b]	16734	1		T13	3		T15	567		T37	1
valid_sources[0x7c]	17536	1		T15	499		T37	1		T43	2
valid_sources[0x7d]	17403	1		T14	3		T15	551		T37	1
valid_sources[0x7e]	17692	1		T14	3		T15	566		T39	3
valid_sources[0x7f]	18202	1		T15	455		T37	5		T42	1
valid_sources[0x80]	17122	1		T13	1		T14	3		T15	545

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1056982

1

T1

1

T2

1

T4

1

values[0x0]

all_enables

biggest_size

1589005

1

T1

7

T2

5

T3

5

values[0x1]

all_enables

biggest_size

1590030

1

T1

5

T2

5

T3

7