Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	611407135	5049444	0	0
wdog_bark_thold_rd_A	611407135	47471	0	0
wdog_bite_thold_rd_A	611407135	42180	0	0
wdog_ctrl_rd_A	611407135	42734	0	0
wdog_regwen_rd_A	611407135	47167	0	0
wkup_ctrl_rd_A	611407135	41282	0	0
wkup_thold_hi_rd_A	611407135	47544	0	0
wkup_thold_lo_rd_A	611407135	41855	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611407135	5049444	0	0
T15	600046	141546	0	0
T16	0	306041	0	0
T17	0	90576	0	0
T23	572634	0	0	0
T30	0	178004	0	0
T31	0	466822	0	0
T32	0	60511	0	0
T33	0	145590	0	0
T34	0	63316	0	0
T35	0	158753	0	0
T36	0	86340	0	0
T37	136212	0	0	0
T38	306562	0	0	0
T39	937113	0	0	0
T40	592244	0	0	0
T41	127645	0	0	0
T42	813493	0	0	0
T43	6824	0	0	0
T44	12830	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611407135	47471	0	0
T15	600046	7971	0	0
T23	572634	0	0	0
T34	0	6034	0	0
T37	136212	0	0	0
T38	306562	0	0	0
T39	937113	0	0	0
T40	592244	0	0	0
T41	127645	0	0	0
T42	813493	0	0	0
T43	6824	0	0	0
T44	12830	0	0	0
T88	0	3082	0	0
T89	0	2035	0	0
T90	0	2681	0	0
T91	0	1403	0	0
T92	0	3672	0	0
T93	0	2662	0	0
T94	0	5689	0	0
T95	0	11144	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611407135	42180	0	0
T15	600046	7333	0	0
T23	572634	0	0	0
T34	0	5157	0	0
T37	136212	0	0	0
T38	306562	0	0	0
T39	937113	0	0	0
T40	592244	0	0	0
T41	127645	0	0	0
T42	813493	0	0	0
T43	6824	0	0	0
T44	12830	0	0	0
T88	0	2743	0	0
T89	0	1658	0	0
T90	0	2530	0	0
T91	0	1252	0	0
T92	0	3316	0	0
T93	0	2313	0	0
T94	0	5105	0	0
T95	0	9849	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611407135	42734	0	0
T15	600046	7111	0	0
T23	572634	0	0	0
T34	0	5237	0	0
T37	136212	0	0	0
T38	306562	0	0	0
T39	937113	0	0	0
T40	592244	0	0	0
T41	127645	0	0	0
T42	813493	0	0	0
T43	6824	0	0	0
T44	12830	0	0	0
T88	0	2899	0	0
T89	0	1818	0	0
T90	0	2528	0	0
T91	0	1389	0	0
T92	0	3571	0	0
T93	0	2280	0	0
T94	0	5115	0	0
T95	0	9851	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611407135	47167	0	0
T15	600046	8300	0	0
T23	572634	0	0	0
T34	0	5722	0	0
T37	136212	0	0	0
T38	306562	0	0	0
T39	937113	0	0	0
T40	592244	0	0	0
T41	127645	0	0	0
T42	813493	0	0	0
T43	6824	0	0	0
T44	12830	0	0	0
T88	0	3047	0	0
T89	0	1836	0	0
T90	0	2973	0	0
T91	0	1536	0	0
T92	0	3697	0	0
T93	0	2339	0	0
T94	0	5580	0	0
T95	0	11113	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611407135	41282	0	0
T15	600046	7243	0	0
T23	572634	0	0	0
T34	0	5226	0	0
T37	136212	0	0	0
T38	306562	0	0	0
T39	937113	0	0	0
T40	592244	0	0	0
T41	127645	0	0	0
T42	813493	0	0	0
T43	6824	0	0	0
T44	12830	0	0	0
T88	0	2517	0	0
T89	0	1493	0	0
T90	0	2352	0	0
T91	0	1401	0	0
T92	0	3164	0	0
T93	0	2309	0	0
T94	0	4491	0	0
T95	0	9970	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611407135	47544	0	0
T15	600046	7924	0	0
T23	572634	0	0	0
T34	0	6120	0	0
T37	136212	0	0	0
T38	306562	0	0	0
T39	937113	0	0	0
T40	592244	0	0	0
T41	127645	0	0	0
T42	813493	0	0	0
T43	6824	0	0	0
T44	12830	0	0	0
T88	0	3008	0	0
T89	0	2053	0	0
T90	0	2687	0	0
T91	0	1580	0	0
T92	0	3715	0	0
T93	0	2508	0	0
T94	0	5747	0	0
T95	0	11093	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611407135	41855	0	0
T15	600046	7309	0	0
T23	572634	0	0	0
T34	0	4976	0	0
T37	136212	0	0	0
T38	306562	0	0	0
T39	937113	0	0	0
T40	592244	0	0	0
T41	127645	0	0	0
T42	813493	0	0	0
T43	6824	0	0	0
T44	12830	0	0	0
T88	0	2675	0	0
T89	0	1887	0	0
T90	0	2527	0	0
T91	0	1237	0	0
T92	0	3124	0	0
T93	0	2203	0	0
T94	0	4953	0	0
T95	0	10031	0	0