Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	389472	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4800971	1		T1	11		T2	13		T3	13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1276182	1		T1	1		T2	1		T3	1
values[0x0]	1835532	1		T1	10		T2	9		T3	8
values[0x1]	2078729	1		T1	9		T2	10		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	173054	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5017389	1		T1	11		T2	14		T3	13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18990	1		T1	2		T4	153		T6	237
valid_sources[0x01]	20893	1		T4	171		T6	282		T8	117
valid_sources[0x02]	20008	1		T4	156		T6	233		T8	9
valid_sources[0x03]	20617	1		T4	180		T6	302		T8	128
valid_sources[0x04]	20602	1		T4	177		T6	227		T8	193
valid_sources[0x05]	20863	1		T4	163		T6	223		T8	279
valid_sources[0x06]	20042	1		T4	144		T6	242		T8	303
valid_sources[0x07]	21179	1		T4	170		T6	232		T8	123
valid_sources[0x08]	22514	1		T4	173		T6	215		T8	233
valid_sources[0x09]	21366	1		T4	177		T6	257		T8	300
valid_sources[0x0a]	19854	1		T4	173		T6	227		T8	301
valid_sources[0x0b]	18879	1		T4	174		T6	226		T8	32
valid_sources[0x0c]	21903	1		T1	1		T4	156		T6	279
valid_sources[0x0d]	19814	1		T4	164		T6	179		T8	539
valid_sources[0x0e]	20091	1		T4	168		T6	225		T8	345
valid_sources[0x0f]	20550	1		T4	177		T6	238		T8	210
valid_sources[0x10]	20193	1		T4	164		T6	214		T7	1
valid_sources[0x11]	19351	1		T4	142		T6	211		T8	92
valid_sources[0x12]	19527	1		T4	194		T6	286		T8	17
valid_sources[0x13]	19736	1		T4	184		T6	282		T8	118
valid_sources[0x14]	20602	1		T4	187		T6	207		T8	260
valid_sources[0x15]	20196	1		T4	168		T6	207		T8	213
valid_sources[0x16]	19484	1		T4	174		T6	179		T7	1
valid_sources[0x17]	18983	1		T4	179		T6	233		T7	1
valid_sources[0x18]	20137	1		T4	166		T6	248		T8	13
valid_sources[0x19]	21476	1		T4	168		T6	260		T8	10
valid_sources[0x1a]	19305	1		T4	186		T6	267		T8	10
valid_sources[0x1b]	20516	1		T4	164		T6	248		T8	309
valid_sources[0x1c]	19545	1		T4	198		T6	320		T8	102
valid_sources[0x1d]	19629	1		T4	178		T6	243		T7	1
valid_sources[0x1e]	21095	1		T4	157		T6	242		T8	458
valid_sources[0x1f]	22362	1		T4	181		T6	259		T8	588
valid_sources[0x20]	20312	1		T4	167		T6	295		T7	1
valid_sources[0x21]	20850	1		T4	154		T6	230		T8	113
valid_sources[0x22]	19313	1		T4	186		T6	319		T7	1
valid_sources[0x23]	18642	1		T1	3		T4	176		T6	255
valid_sources[0x24]	21447	1		T4	192		T6	247		T8	401
valid_sources[0x25]	20413	1		T4	169		T6	237		T8	124
valid_sources[0x26]	19736	1		T4	184		T6	242		T8	160
valid_sources[0x27]	19989	1		T4	176		T6	196		T8	281
valid_sources[0x28]	20035	1		T4	136		T6	253		T8	312
valid_sources[0x29]	18795	1		T4	145		T6	222		T8	139
valid_sources[0x2a]	20111	1		T4	169		T6	180		T8	148
valid_sources[0x2b]	20968	1		T4	183		T6	215		T8	136
valid_sources[0x2c]	20587	1		T4	151		T6	260		T8	11
valid_sources[0x2d]	20493	1		T4	159		T6	242		T7	1
valid_sources[0x2e]	20410	1		T4	180		T6	275		T8	190
valid_sources[0x2f]	21358	1		T4	139		T6	304		T8	239
valid_sources[0x30]	18988	1		T4	153		T6	242		T8	170
valid_sources[0x31]	20269	1		T4	138		T6	277		T8	12
valid_sources[0x32]	19045	1		T4	144		T6	277		T8	10
valid_sources[0x33]	21471	1		T4	200		T5	20		T6	224
valid_sources[0x34]	20209	1		T4	178		T6	180		T8	276
valid_sources[0x35]	20463	1		T4	195		T6	248		T7	1
valid_sources[0x36]	21034	1		T4	158		T6	285		T8	316
valid_sources[0x37]	20379	1		T4	150		T6	211		T8	9
valid_sources[0x38]	20232	1		T4	196		T6	235		T8	592
valid_sources[0x39]	20207	1		T2	2		T4	148		T6	290
valid_sources[0x3a]	19923	1		T4	183		T6	198		T8	119
valid_sources[0x3b]	19535	1		T4	203		T6	282		T8	130
valid_sources[0x3c]	20152	1		T4	183		T6	293		T8	35
valid_sources[0x3d]	19861	1		T1	2		T4	159		T6	321
valid_sources[0x3e]	20095	1		T4	179		T6	222		T8	364
valid_sources[0x3f]	20647	1		T4	182		T6	256		T8	10
valid_sources[0x40]	20722	1		T4	176		T6	199		T8	164
valid_sources[0x41]	20164	1		T4	157		T6	230		T8	189
valid_sources[0x42]	19341	1		T4	175		T6	321		T8	187
valid_sources[0x43]	21071	1		T4	170		T6	225		T8	361
valid_sources[0x44]	19879	1		T4	182		T6	270		T8	127
valid_sources[0x45]	20931	1		T4	173		T6	235		T8	380
valid_sources[0x46]	20389	1		T4	178		T6	272		T8	386
valid_sources[0x47]	20227	1		T4	145		T6	263		T8	275
valid_sources[0x48]	20538	1		T4	158		T6	290		T8	81
valid_sources[0x49]	20057	1		T4	179		T6	323		T8	214
valid_sources[0x4a]	20003	1		T4	187		T6	293		T8	739
valid_sources[0x4b]	18586	1		T4	142		T6	287		T8	143
valid_sources[0x4c]	19961	1		T4	146		T6	248		T8	2
valid_sources[0x4d]	19183	1		T4	161		T6	262		T8	12
valid_sources[0x4e]	20717	1		T4	179		T6	275		T8	64
valid_sources[0x4f]	20329	1		T4	168		T6	210		T8	3
valid_sources[0x50]	21569	1		T4	189		T6	242		T8	273
valid_sources[0x51]	20035	1		T4	171		T6	232		T8	109
valid_sources[0x52]	20617	1		T4	151		T6	267		T8	122
valid_sources[0x53]	20534	1		T4	179		T6	214		T8	366
valid_sources[0x54]	19799	1		T4	171		T6	302		T8	48
valid_sources[0x55]	20369	1		T4	141		T6	303		T8	82
valid_sources[0x56]	20451	1		T4	164		T6	227		T8	206
valid_sources[0x57]	20165	1		T4	195		T6	201		T8	109
valid_sources[0x58]	19761	1		T1	1		T4	162		T6	268
valid_sources[0x59]	19376	1		T4	159		T6	212		T8	254
valid_sources[0x5a]	20727	1		T1	1		T4	167		T6	351
valid_sources[0x5b]	19615	1		T4	142		T6	284		T8	146
valid_sources[0x5c]	19982	1		T1	1		T4	182		T6	286
valid_sources[0x5d]	19154	1		T4	174		T6	207		T8	99
valid_sources[0x5e]	21365	1		T4	155		T6	284		T8	855
valid_sources[0x5f]	20413	1		T4	156		T6	234		T8	97
valid_sources[0x60]	21163	1		T4	173		T6	245		T8	39
valid_sources[0x61]	19520	1		T4	180		T6	231		T8	11
valid_sources[0x62]	21164	1		T1	1		T4	156		T6	270
valid_sources[0x63]	20697	1		T4	175		T6	239		T8	92
valid_sources[0x64]	18842	1		T4	183		T6	225		T8	342
valid_sources[0x65]	19780	1		T4	187		T6	250		T8	6
valid_sources[0x66]	20917	1		T4	189		T6	178		T8	213
valid_sources[0x67]	21395	1		T4	163		T6	255		T8	117
valid_sources[0x68]	20292	1		T4	160		T6	217		T8	232
valid_sources[0x69]	21303	1		T2	1		T4	168		T6	291
valid_sources[0x6a]	20186	1		T4	158		T6	253		T8	304
valid_sources[0x6b]	20304	1		T4	176		T6	266		T8	245
valid_sources[0x6c]	20496	1		T4	146		T6	368		T8	79
valid_sources[0x6d]	19802	1		T4	147		T6	236		T8	169
valid_sources[0x6e]	19306	1		T1	1		T4	132		T6	254
valid_sources[0x6f]	20635	1		T4	181		T6	252		T8	212
valid_sources[0x70]	19606	1		T4	188		T6	285		T7	2
valid_sources[0x71]	20645	1		T2	1		T4	170		T6	235
valid_sources[0x72]	20256	1		T4	189		T6	247		T8	526
valid_sources[0x73]	21068	1		T4	172		T6	272		T8	88
valid_sources[0x74]	21421	1		T4	175		T6	190		T8	8
valid_sources[0x75]	19419	1		T2	1		T4	151		T6	272
valid_sources[0x76]	20822	1		T4	158		T6	296		T8	197
valid_sources[0x77]	20900	1		T4	183		T6	237		T8	14
valid_sources[0x78]	20816	1		T4	148		T6	244		T8	163
valid_sources[0x79]	19529	1		T2	1		T4	150		T6	222
valid_sources[0x7a]	20754	1		T4	177		T6	216		T8	171
valid_sources[0x7b]	20924	1		T4	182		T6	251		T7	1
valid_sources[0x7c]	20069	1		T4	178		T6	152		T8	9
valid_sources[0x7d]	20370	1		T3	19		T4	191		T6	240
valid_sources[0x7e]	19375	1		T4	165		T6	193		T8	21
valid_sources[0x7f]	20194	1		T4	166		T6	234		T8	175
valid_sources[0x80]	19656	1		T4	191		T6	303		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1197672

1

T1

1

T2

1

T4

10121

values[0x0]

all_enables

biggest_size

1802938

1

T1

4

T2

6

T3

5

values[0x1]

all_enables

biggest_size

1800361

1

T1

6

T2

6

T3

8