Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	701631205	5650310	0	0
wdog_bark_thold_rd_A	701631205	99714	0	0
wdog_bite_thold_rd_A	701631205	85369	0	0
wdog_ctrl_rd_A	701631205	85338	0	0
wdog_regwen_rd_A	701631205	98501	0	0
wkup_ctrl_rd_A	701631205	87251	0	0
wkup_thold_hi_rd_A	701631205	97390	0	0
wkup_thold_lo_rd_A	701631205	86143	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701631205	5650310	0	0
T4	125489	44938	0	0
T5	243163	0	0	0
T6	308475	64153	0	0
T7	11411	0	0	0
T8	159625	51709	0	0
T9	38798	0	0	0
T10	37523	0	0	0
T11	78964	0	0	0
T12	48254	0	0	0
T13	8650	0	0	0
T15	0	138380	0	0
T16	0	43829	0	0
T35	0	62628	0	0
T36	0	166374	0	0
T37	0	148557	0	0
T38	0	176274	0	0
T39	0	123857	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701631205	99714	0	0
T6	308475	6716	0	0
T7	11411	0	0	0
T8	159625	0	0	0
T9	38798	0	0	0
T10	37523	0	0	0
T11	78964	0	0	0
T12	48254	0	0	0
T13	8650	0	0	0
T14	771305	0	0	0
T23	40171	0	0	0
T81	0	6656	0	0
T85	0	13192	0	0
T86	0	5130	0	0
T87	0	12294	0	0
T88	0	15805	0	0
T89	0	4030	0	0
T90	0	12833	0	0
T91	0	14325	0	0
T92	0	7552	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701631205	85369	0	0
T6	308475	5973	0	0
T7	11411	0	0	0
T8	159625	0	0	0
T9	38798	0	0	0
T10	37523	0	0	0
T11	78964	0	0	0
T12	48254	0	0	0
T13	8650	0	0	0
T14	771305	0	0	0
T23	40171	0	0	0
T81	0	5900	0	0
T85	0	11160	0	0
T86	0	4335	0	0
T87	0	10489	0	0
T88	0	13431	0	0
T89	0	3678	0	0
T90	0	10754	0	0
T91	0	11983	0	0
T92	0	6656	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701631205	85338	0	0
T6	308475	5846	0	0
T7	11411	0	0	0
T8	159625	0	0	0
T9	38798	0	0	0
T10	37523	0	0	0
T11	78964	0	0	0
T12	48254	0	0	0
T13	8650	0	0	0
T14	771305	0	0	0
T23	40171	0	0	0
T81	0	6053	0	0
T85	0	11216	0	0
T86	0	4276	0	0
T87	0	10257	0	0
T88	0	13686	0	0
T89	0	3491	0	0
T90	0	11268	0	0
T91	0	11835	0	0
T92	0	6360	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701631205	98501	0	0
T6	308475	6325	0	0
T7	11411	0	0	0
T8	159625	0	0	0
T9	38798	0	0	0
T10	37523	0	0	0
T11	78964	0	0	0
T12	48254	0	0	0
T13	8650	0	0	0
T14	771305	0	0	0
T23	40171	0	0	0
T81	0	6946	0	0
T85	0	12921	0	0
T86	0	4936	0	0
T87	0	12027	0	0
T88	0	15533	0	0
T89	0	3945	0	0
T90	0	12914	0	0
T91	0	13865	0	0
T92	0	7556	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701631205	87251	0	0
T6	308475	5716	0	0
T7	11411	0	0	0
T8	159625	0	0	0
T9	38798	0	0	0
T10	37523	0	0	0
T11	78964	0	0	0
T12	48254	0	0	0
T13	8650	0	0	0
T14	771305	0	0	0
T23	40171	0	0	0
T81	0	6213	0	0
T85	0	11478	0	0
T86	0	4053	0	0
T87	0	10477	0	0
T88	0	14006	0	0
T89	0	3694	0	0
T90	0	11382	0	0
T91	0	12294	0	0
T92	0	6811	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701631205	97390	0	0
T6	308475	6636	0	0
T7	11411	0	0	0
T8	159625	0	0	0
T9	38798	0	0	0
T10	37523	0	0	0
T11	78964	0	0	0
T12	48254	0	0	0
T13	8650	0	0	0
T14	771305	0	0	0
T23	40171	0	0	0
T81	0	6634	0	0
T85	0	12515	0	0
T86	0	5022	0	0
T87	0	11751	0	0
T88	0	15793	0	0
T89	0	4198	0	0
T90	0	12274	0	0
T91	0	14024	0	0
T92	0	7463	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	701631205	86143	0	0
T6	308475	5633	0	0
T7	11411	0	0	0
T8	159625	0	0	0
T9	38798	0	0	0
T10	37523	0	0	0
T11	78964	0	0	0
T12	48254	0	0	0
T13	8650	0	0	0
T14	771305	0	0	0
T23	40171	0	0	0
T81	0	6242	0	0
T85	0	11605	0	0
T86	0	4120	0	0
T87	0	10530	0	0
T88	0	13765	0	0
T89	0	3611	0	0
T90	0	11189	0	0
T91	0	11843	0	0
T92	0	6485	0	0