Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	334620	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4087492	1		T1	136835		T2	13		T3	12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1085873	1		T1	36070		T2	1		T3	1
values[0x0]	1564461	1		T1	52033		T2	9		T3	11
values[0x1]	1771778	1		T1	59413		T2	9		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149316	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4272796	1		T1	142927		T2	13		T3	13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17015	1		T1	589		T4	623		T6	8
valid_sources[0x01]	17299	1		T1	541		T4	569		T9	138
valid_sources[0x02]	17178	1		T1	612		T4	652		T6	1
valid_sources[0x03]	17135	1		T1	607		T2	1		T4	609
valid_sources[0x04]	17550	1		T1	493		T4	637		T6	2
valid_sources[0x05]	17462	1		T1	533		T4	642		T9	117
valid_sources[0x06]	18271	1		T1	573		T4	713		T8	1
valid_sources[0x07]	18297	1		T1	559		T4	740		T9	113
valid_sources[0x08]	17240	1		T1	600		T4	628		T9	144
valid_sources[0x09]	17217	1		T1	542		T4	615		T8	1
valid_sources[0x0a]	17372	1		T1	537		T4	553		T6	3
valid_sources[0x0b]	16423	1		T1	539		T3	20		T4	556
valid_sources[0x0c]	16508	1		T1	584		T4	621		T9	118
valid_sources[0x0d]	17255	1		T1	641		T4	653		T6	4
valid_sources[0x0e]	18116	1		T1	642		T4	629		T8	3
valid_sources[0x0f]	19645	1		T1	674		T2	1		T4	648
valid_sources[0x10]	16686	1		T1	514		T4	658		T9	130
valid_sources[0x11]	17583	1		T1	493		T4	652		T8	1
valid_sources[0x12]	16928	1		T1	550		T4	550		T8	1
valid_sources[0x13]	16704	1		T1	645		T4	608		T8	1
valid_sources[0x14]	16893	1		T1	568		T4	684		T8	1
valid_sources[0x15]	17090	1		T1	517		T4	688		T6	4
valid_sources[0x16]	17881	1		T1	626		T4	575		T6	2
valid_sources[0x17]	17763	1		T1	571		T4	661		T9	131
valid_sources[0x18]	18142	1		T1	592		T4	680		T8	2
valid_sources[0x19]	16846	1		T1	536		T4	573		T6	6
valid_sources[0x1a]	17056	1		T1	603		T4	606		T6	4
valid_sources[0x1b]	16454	1		T1	592		T4	649		T8	2
valid_sources[0x1c]	16535	1		T1	559		T4	586		T6	5
valid_sources[0x1d]	18235	1		T1	558		T2	1		T4	763
valid_sources[0x1e]	18586	1		T1	583		T4	598		T9	146
valid_sources[0x1f]	17044	1		T1	554		T4	595		T9	144
valid_sources[0x20]	17010	1		T1	535		T4	681		T8	2
valid_sources[0x21]	16860	1		T1	613		T4	587		T8	4
valid_sources[0x22]	16916	1		T1	621		T4	652		T6	1
valid_sources[0x23]	17184	1		T1	598		T4	671		T8	2
valid_sources[0x24]	18043	1		T1	584		T4	556		T9	123
valid_sources[0x25]	16675	1		T1	532		T4	638		T8	2
valid_sources[0x26]	17370	1		T1	601		T4	668		T9	116
valid_sources[0x27]	17708	1		T1	552		T4	633		T9	122
valid_sources[0x28]	17721	1		T1	700		T4	600		T6	4
valid_sources[0x29]	18716	1		T1	560		T4	664		T9	124
valid_sources[0x2a]	16398	1		T1	557		T4	616		T6	2
valid_sources[0x2b]	17011	1		T1	594		T4	657		T6	2
valid_sources[0x2c]	16476	1		T1	591		T4	664		T8	1
valid_sources[0x2d]	18171	1		T1	573		T4	732		T6	1
valid_sources[0x2e]	17320	1		T1	579		T4	552		T9	116
valid_sources[0x2f]	19321	1		T1	679		T4	650		T9	121
valid_sources[0x30]	17449	1		T1	592		T4	641		T6	6
valid_sources[0x31]	16427	1		T1	620		T4	645		T8	5
valid_sources[0x32]	17165	1		T1	614		T4	695		T9	129
valid_sources[0x33]	16045	1		T1	547		T4	594		T8	4
valid_sources[0x34]	16632	1		T1	536		T4	653		T8	1
valid_sources[0x35]	17825	1		T1	614		T4	690		T6	1
valid_sources[0x36]	18666	1		T1	567		T4	618		T6	1
valid_sources[0x37]	17863	1		T1	559		T4	684		T6	2
valid_sources[0x38]	17273	1		T1	607		T4	650		T8	3
valid_sources[0x39]	17366	1		T1	608		T4	633		T9	107
valid_sources[0x3a]	15699	1		T1	529		T2	1		T4	641
valid_sources[0x3b]	17781	1		T1	481		T4	694		T6	1
valid_sources[0x3c]	18123	1		T1	580		T4	625		T6	1
valid_sources[0x3d]	17643	1		T1	601		T4	572		T9	122
valid_sources[0x3e]	16689	1		T1	489		T4	672		T6	1
valid_sources[0x3f]	16606	1		T1	549		T2	1		T4	687
valid_sources[0x40]	17391	1		T1	552		T4	564		T8	2
valid_sources[0x41]	18610	1		T1	478		T4	626		T8	5
valid_sources[0x42]	17112	1		T1	515		T4	589		T6	2
valid_sources[0x43]	17008	1		T1	593		T4	663		T6	7
valid_sources[0x44]	15990	1		T1	570		T4	656		T6	2
valid_sources[0x45]	18411	1		T1	539		T4	642		T8	2
valid_sources[0x46]	16210	1		T1	578		T4	609		T8	2
valid_sources[0x47]	17489	1		T1	515		T4	564		T9	125
valid_sources[0x48]	16826	1		T1	643		T4	618		T9	84
valid_sources[0x49]	17714	1		T1	656		T4	706		T9	125
valid_sources[0x4a]	17312	1		T1	514		T4	607		T6	2
valid_sources[0x4b]	17273	1		T1	579		T4	649		T9	124
valid_sources[0x4c]	16241	1		T1	520		T4	626		T9	139
valid_sources[0x4d]	17382	1		T1	640		T4	673		T6	1
valid_sources[0x4e]	16968	1		T1	549		T4	620		T9	135
valid_sources[0x4f]	17157	1		T1	619		T4	589		T6	1
valid_sources[0x50]	17637	1		T1	549		T4	669		T9	129
valid_sources[0x51]	17992	1		T1	587		T4	662		T9	160
valid_sources[0x52]	18226	1		T1	596		T4	625		T6	1
valid_sources[0x53]	16340	1		T1	570		T4	696		T8	2
valid_sources[0x54]	15862	1		T1	558		T4	639		T8	3
valid_sources[0x55]	16773	1		T1	611		T4	632		T8	3
valid_sources[0x56]	17005	1		T1	569		T4	573		T6	1
valid_sources[0x57]	18588	1		T1	576		T4	607		T8	1
valid_sources[0x58]	18708	1		T1	611		T4	704		T9	123
valid_sources[0x59]	18151	1		T1	530		T2	1		T4	613
valid_sources[0x5a]	17202	1		T1	559		T4	557		T6	3
valid_sources[0x5b]	17357	1		T1	532		T4	699		T6	1
valid_sources[0x5c]	15811	1		T1	564		T4	604		T8	1
valid_sources[0x5d]	17829	1		T1	597		T4	643		T9	123
valid_sources[0x5e]	15725	1		T1	515		T4	619		T9	106
valid_sources[0x5f]	16622	1		T1	497		T4	649		T6	1
valid_sources[0x60]	16335	1		T1	499		T4	639		T5	9
valid_sources[0x61]	16368	1		T1	576		T4	645		T9	135
valid_sources[0x62]	16793	1		T1	579		T4	638		T8	3
valid_sources[0x63]	18425	1		T1	632		T4	680		T9	144
valid_sources[0x64]	17762	1		T1	526		T4	611		T8	2
valid_sources[0x65]	16226	1		T1	635		T4	667		T6	2
valid_sources[0x66]	16913	1		T1	545		T4	654		T6	1
valid_sources[0x67]	16868	1		T1	520		T4	599		T6	2
valid_sources[0x68]	17414	1		T1	616		T4	616		T6	8
valid_sources[0x69]	16431	1		T1	538		T4	619		T8	2
valid_sources[0x6a]	18313	1		T1	531		T4	702		T6	10
valid_sources[0x6b]	17078	1		T1	554		T4	688		T8	3
valid_sources[0x6c]	17077	1		T1	628		T4	601		T8	1
valid_sources[0x6d]	16874	1		T1	538		T4	667		T6	2
valid_sources[0x6e]	17673	1		T1	577		T4	643		T6	3
valid_sources[0x6f]	16236	1		T1	587		T4	709		T9	152
valid_sources[0x70]	16916	1		T1	501		T4	665		T9	118
valid_sources[0x71]	17761	1		T1	564		T4	660		T9	131
valid_sources[0x72]	16729	1		T1	559		T4	589		T6	7
valid_sources[0x73]	16388	1		T1	645		T4	680		T9	146
valid_sources[0x74]	16534	1		T1	528		T4	629		T9	123
valid_sources[0x75]	15974	1		T1	574		T4	604		T8	1
valid_sources[0x76]	17485	1		T1	565		T4	662		T8	1
valid_sources[0x77]	18099	1		T1	609		T4	610		T6	5
valid_sources[0x78]	17968	1		T1	512		T4	693		T6	12
valid_sources[0x79]	17328	1		T1	586		T4	581		T8	2
valid_sources[0x7a]	16984	1		T1	539		T2	1		T4	593
valid_sources[0x7b]	17950	1		T1	505		T4	666		T5	3
valid_sources[0x7c]	17063	1		T1	594		T2	1		T4	581
valid_sources[0x7d]	17207	1		T1	612		T4	680		T8	2
valid_sources[0x7e]	17524	1		T1	569		T4	614		T8	3
valid_sources[0x7f]	16879	1		T1	599		T4	629		T6	5
valid_sources[0x80]	18721	1		T1	451		T4	646		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1018812

1

T1

34029

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1535784

1

T1

51203

T2

6

T3

6

values[0x1]

all_enables

biggest_size

1532896

1

T1

51603

T2

6

T3

5