Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	646182817	4817190	0	0
wdog_bark_thold_rd_A	646182817	78101	0	0
wdog_bite_thold_rd_A	646182817	68628	0	0
wdog_ctrl_rd_A	646182817	68257	0	0
wdog_regwen_rd_A	646182817	79864	0	0
wkup_ctrl_rd_A	646182817	68553	0	0
wkup_thold_hi_rd_A	646182817	79419	0	0
wkup_thold_lo_rd_A	646182817	69023	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646182817	4817190	0	0
T1	623121	164060	0	0
T2	8749	0	0	0
T3	817152	0	0	0
T4	752480	183349	0	0
T5	23647	0	0	0
T6	106565	0	0	0
T7	235174	0	0	0
T8	296108	0	0	0
T9	104227	32677	0	0
T10	453150	0	0	0
T19	0	81377	0	0
T22	0	79995	0	0
T35	0	66195	0	0
T36	0	5351	0	0
T37	0	57834	0	0
T38	0	302170	0	0
T39	0	115987	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646182817	78101	0	0
T4	752480	10036	0	0
T5	23647	0	0	0
T6	106565	0	0	0
T7	235174	0	0	0
T8	296108	0	0	0
T9	104227	0	0	0
T10	453150	0	0	0
T11	790210	0	0	0
T26	35974	0	0	0
T27	36995	0	0	0
T93	0	4052	0	0
T94	0	4806	0	0
T95	0	4891	0	0
T96	0	11528	0	0
T97	0	3690	0	0
T98	0	5146	0	0
T99	0	3389	0	0
T100	0	2256	0	0
T101	0	5447	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646182817	68628	0	0
T4	752480	8695	0	0
T5	23647	0	0	0
T6	106565	0	0	0
T7	235174	0	0	0
T8	296108	0	0	0
T9	104227	0	0	0
T10	453150	0	0	0
T11	790210	0	0	0
T26	35974	0	0	0
T27	36995	0	0	0
T93	0	3594	0	0
T94	0	4416	0	0
T95	0	3923	0	0
T96	0	9925	0	0
T97	0	3165	0	0
T98	0	4569	0	0
T99	0	3366	0	0
T100	0	2218	0	0
T101	0	4662	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646182817	68257	0	0
T4	752480	8483	0	0
T5	23647	0	0	0
T6	106565	0	0	0
T7	235174	0	0	0
T8	296108	0	0	0
T9	104227	0	0	0
T10	453150	0	0	0
T11	790210	0	0	0
T26	35974	0	0	0
T27	36995	0	0	0
T93	0	3464	0	0
T94	0	4185	0	0
T95	0	4264	0	0
T96	0	9300	0	0
T97	0	3124	0	0
T98	0	4500	0	0
T99	0	3093	0	0
T100	0	2298	0	0
T101	0	4950	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646182817	79864	0	0
T4	752480	9550	0	0
T5	23647	0	0	0
T6	106565	0	0	0
T7	235174	0	0	0
T8	296108	0	0	0
T9	104227	0	0	0
T10	453150	0	0	0
T11	790210	0	0	0
T26	35974	0	0	0
T27	36995	0	0	0
T93	0	4357	0	0
T94	0	5046	0	0
T95	0	4683	0	0
T96	0	11262	0	0
T97	0	3808	0	0
T98	0	4979	0	0
T99	0	3590	0	0
T100	0	2529	0	0
T101	0	5741	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646182817	68553	0	0
T4	752480	8689	0	0
T5	23647	0	0	0
T6	106565	0	0	0
T7	235174	0	0	0
T8	296108	0	0	0
T9	104227	0	0	0
T10	453150	0	0	0
T11	790210	0	0	0
T26	35974	0	0	0
T27	36995	0	0	0
T93	0	3295	0	0
T94	0	4331	0	0
T95	0	3865	0	0
T96	0	9727	0	0
T97	0	3332	0	0
T98	0	4436	0	0
T99	0	2920	0	0
T100	0	2123	0	0
T101	0	5320	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646182817	79419	0	0
T4	752480	9826	0	0
T5	23647	0	0	0
T6	106565	0	0	0
T7	235174	0	0	0
T8	296108	0	0	0
T9	104227	0	0	0
T10	453150	0	0	0
T11	790210	0	0	0
T26	35974	0	0	0
T27	36995	0	0	0
T93	0	4452	0	0
T94	0	5000	0	0
T95	0	4575	0	0
T96	0	11095	0	0
T97	0	3702	0	0
T98	0	5269	0	0
T99	0	3420	0	0
T100	0	2403	0	0
T101	0	6069	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646182817	69023	0	0
T4	752480	8736	0	0
T5	23647	0	0	0
T6	106565	0	0	0
T7	235174	0	0	0
T8	296108	0	0	0
T9	104227	0	0	0
T10	453150	0	0	0
T11	790210	0	0	0
T26	35974	0	0	0
T27	36995	0	0	0
T93	0	3464	0	0
T94	0	4523	0	0
T95	0	4138	0	0
T96	0	9852	0	0
T97	0	3247	0	0
T98	0	4742	0	0
T99	0	3065	0	0
T100	0	2285	0	0
T101	0	4786	0	0