Module Definition
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Module Instance : tb.dut.u_reg.u_wkup_count_hi_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 100.00 71.43 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.10 94.74 71.83 89.83 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 74.06 92.86 67.35 86.05 50.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_lo_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.11 100.00 90.14 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.36 100.00 87.76 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_count_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.21 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.11 100.00 90.14 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.36 100.00 87.76 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_cause_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.44 100.00 93.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.18 100.00 90.41 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.57 100.00 98.28 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.36 100.00 87.76 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 + DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :
SCORECOND
97.73 90.91
tb.dut.u_reg.u_wkup_ctrl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_wkup_thold_hi_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_wkup_thold_lo_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_wdog_bark_thold_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_wdog_bite_thold_cdc

SCORECOND
92.86 71.43
tb.dut.u_reg.u_wkup_count_hi_cdc

SCORECOND
98.21 92.86
tb.dut.u_reg.u_wkup_count_lo_cdc

SCORECOND
98.21 92.86
tb.dut.u_reg.u_wdog_count_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_wdog_ctrl_cdc

TotalCoveredPercent
Conditions141392.86
Logical141392.86
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T3,T4

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
SCORECOND
98.44 93.75
tb.dut.u_reg.u_wkup_cause_cdc

TotalCoveredPercent
Conditions161593.75
Logical161593.75
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT28,T30,T32

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T6
11CoveredT1,T2,T3

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 2147483647 39846106 0 0
DstReqKnown_A 31107980 30135550 0 0
SrcAckBusyChk_A 2147483647 47360 0 0
SrcBusyKnown_A 2147483647 2147483647 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 39846106 0 0
T1 6231210 657219 0 0
T2 87490 5359 0 0
T3 8171520 21326 0 0
T4 7524800 328115 0 0
T5 236470 12146 0 0
T6 1065650 310469 0 0
T7 2351740 12222 0 0
T8 2961080 26824 0 0
T9 1042270 600868 0 0
T10 4531500 75859 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31107980 30135550 0 0
T1 249240 247860 0 0
T2 950 170 0 0
T3 24380 23790 0 0
T4 601970 600670 0 0
T5 1030 170 0 0
T6 222000 212130 0 0
T7 9590 8710 0 0
T8 846010 841080 0 0
T9 21250 20340 0 0
T10 377610 366420 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 47360 0 0
T1 6231210 757 0 0
T2 87490 15 0 0
T3 8171520 16 0 0
T4 7524800 792 0 0
T5 236470 15 0 0
T6 1065650 178 0 0
T7 2351740 16 0 0
T8 2961080 242 0 0
T9 1042270 362 0 0
T10 4531500 178 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6231210 6214660 0 0
T2 87490 86820 0 0
T3 8171520 8170700 0 0
T4 7524800 7517120 0 0
T5 236470 235780 0 0
T6 1065650 1065560 0 0
T7 2351740 2350840 0 0
T8 2961080 2960540 0 0
T9 1042270 1031410 0 0
T10 4531500 4530500 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_hi_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 646182817 5382362 0 0
DstReqKnown_A 3110798 3013555 0 0
SrcAckBusyChk_A 646182817 6387 0 0
SrcBusyKnown_A 646182817 645546591 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 5382362 0 0
T1 623121 96582 0 0
T2 8749 615 0 0
T3 817152 2666 0 0
T4 752480 47156 0 0
T5 23647 1503 0 0
T6 106565 43463 0 0
T7 235174 1627 0 0
T8 296108 3754 0 0
T9 104227 85449 0 0
T10 453150 10365 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3110798 3013555 0 0
T1 24924 24786 0 0
T2 95 17 0 0
T3 2438 2379 0 0
T4 60197 60067 0 0
T5 103 17 0 0
T6 22200 21213 0 0
T7 959 871 0 0
T8 84601 84108 0 0
T9 2125 2034 0 0
T10 37761 36642 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 6387 0 0
T1 623121 108 0 0
T2 8749 2 0 0
T3 817152 2 0 0
T4 752480 112 0 0
T5 23647 2 0 0
T6 106565 26 0 0
T7 235174 2 0 0
T8 296108 33 0 0
T9 104227 51 0 0
T10 453150 24 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 645546591 0 0
T1 623121 621466 0 0
T2 8749 8682 0 0
T3 817152 817070 0 0
T4 752480 751712 0 0
T5 23647 23578 0 0
T6 106565 106556 0 0
T7 235174 235084 0 0
T8 296108 296054 0 0
T9 104227 103141 0 0
T10 453150 453050 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_ctrl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 646182817 5390296 0 0
DstReqKnown_A 3110798 3013555 0 0
SrcAckBusyChk_A 646182817 6530 0 0
SrcBusyKnown_A 646182817 645546591 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 5390296 0 0
T1 623121 90310 0 0
T2 8749 611 0 0
T3 817152 4000 0 0
T4 752480 47531 0 0
T5 23647 1479 0 0
T6 106565 42657 0 0
T7 235174 2322 0 0
T8 296108 4317 0 0
T9 104227 81289 0 0
T10 453150 12181 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3110798 3013555 0 0
T1 24924 24786 0 0
T2 95 17 0 0
T3 2438 2379 0 0
T4 60197 60067 0 0
T5 103 17 0 0
T6 22200 21213 0 0
T7 959 871 0 0
T8 84601 84108 0 0
T9 2125 2034 0 0
T10 37761 36642 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 6530 0 0
T1 623121 105 0 0
T2 8749 2 0 0
T3 817152 3 0 0
T4 752480 114 0 0
T5 23647 2 0 0
T6 106565 26 0 0
T7 235174 3 0 0
T8 296108 38 0 0
T9 104227 50 0 0
T10 453150 29 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 645546591 0 0
T1 623121 621466 0 0
T2 8749 8682 0 0
T3 817152 817070 0 0
T4 752480 751712 0 0
T5 23647 23578 0 0
T6 106565 106556 0 0
T7 235174 235084 0 0
T8 296108 296054 0 0
T9 104227 103141 0 0
T10 453150 453050 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 646182817 2638727 0 0
DstReqKnown_A 3110798 3013555 0 0
SrcAckBusyChk_A 646182817 3297 0 0
SrcBusyKnown_A 646182817 645546591 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 2638727 0 0
T1 623121 39068 0 0
T2 8749 351 0 0
T3 817152 1331 0 0
T4 752480 19396 0 0
T5 23647 846 0 0
T6 106565 17809 0 0
T7 235174 666 0 0
T8 296108 1579 0 0
T9 104227 36081 0 0
T10 453150 4435 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3110798 3013555 0 0
T1 24924 24786 0 0
T2 95 17 0 0
T3 2438 2379 0 0
T4 60197 60067 0 0
T5 103 17 0 0
T6 22200 21213 0 0
T7 959 871 0 0
T8 84601 84108 0 0
T9 2125 2034 0 0
T10 37761 36642 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 3297 0 0
T1 623121 49 0 0
T2 8749 1 0 0
T3 817152 1 0 0
T4 752480 51 0 0
T5 23647 1 0 0
T6 106565 11 0 0
T7 235174 1 0 0
T8 296108 15 0 0
T9 104227 24 0 0
T10 453150 11 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 645546591 0 0
T1 623121 621466 0 0
T2 8749 8682 0 0
T3 817152 817070 0 0
T4 752480 751712 0 0
T5 23647 23578 0 0
T6 106565 106556 0 0
T7 235174 235084 0 0
T8 296108 296054 0 0
T9 104227 103141 0 0
T10 453150 453050 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 646182817 2676531 0 0
DstReqKnown_A 3110798 3013555 0 0
SrcAckBusyChk_A 646182817 3330 0 0
SrcBusyKnown_A 646182817 645546591 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 2676531 0 0
T1 623121 38459 0 0
T2 8749 353 0 0
T3 817152 1333 0 0
T4 752480 19127 0 0
T5 23647 853 0 0
T6 106565 17911 0 0
T7 235174 678 0 0
T8 296108 1480 0 0
T9 104227 36133 0 0
T10 453150 4457 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3110798 3013555 0 0
T1 24924 24786 0 0
T2 95 17 0 0
T3 2438 2379 0 0
T4 60197 60067 0 0
T5 103 17 0 0
T6 22200 21213 0 0
T7 959 871 0 0
T8 84601 84108 0 0
T9 2125 2034 0 0
T10 37761 36642 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 3330 0 0
T1 623121 49 0 0
T2 8749 1 0 0
T3 817152 1 0 0
T4 752480 51 0 0
T5 23647 1 0 0
T6 106565 11 0 0
T7 235174 1 0 0
T8 296108 15 0 0
T9 104227 24 0 0
T10 453150 11 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 645546591 0 0
T1 623121 621466 0 0
T2 8749 8682 0 0
T3 817152 817070 0 0
T4 752480 751712 0 0
T5 23647 23578 0 0
T6 106565 106556 0 0
T7 235174 235084 0 0
T8 296108 296054 0 0
T9 104227 103141 0 0
T10 453150 453050 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_ctrl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 646182817 4702535 0 0
DstReqKnown_A 3110798 3013555 0 0
SrcAckBusyChk_A 646182817 5662 0 0
SrcBusyKnown_A 646182817 645546591 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 4702535 0 0
T1 623121 77302 0 0
T2 8749 607 0 0
T3 817152 2673 0 0
T4 752480 39616 0 0
T5 23647 1466 0 0
T6 106565 35573 0 0
T7 235174 1680 0 0
T8 296108 3268 0 0
T9 104227 70267 0 0
T10 453150 9186 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3110798 3013555 0 0
T1 24924 24786 0 0
T2 95 17 0 0
T3 2438 2379 0 0
T4 60197 60067 0 0
T5 103 17 0 0
T6 22200 21213 0 0
T7 959 871 0 0
T8 84601 84108 0 0
T9 2125 2034 0 0
T10 37761 36642 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 5662 0 0
T1 623121 90 0 0
T2 8749 2 0 0
T3 817152 2 0 0
T4 752480 94 0 0
T5 23647 2 0 0
T6 106565 22 0 0
T7 235174 2 0 0
T8 296108 30 0 0
T9 104227 43 0 0
T10 453150 22 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 645546591 0 0
T1 623121 621466 0 0
T2 8749 8682 0 0
T3 817152 817070 0 0
T4 752480 751712 0 0
T5 23647 23578 0 0
T6 106565 106556 0 0
T7 235174 235084 0 0
T8 296108 296054 0 0
T9 104227 103141 0 0
T10 453150 453050 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 646182817 2638371 0 0
DstReqKnown_A 3110798 3013555 0 0
SrcAckBusyChk_A 646182817 3287 0 0
SrcBusyKnown_A 646182817 645546591 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 2638371 0 0
T1 623121 39612 0 0
T2 8749 349 0 0
T3 817152 1329 0 0
T4 752480 19520 0 0
T5 23647 837 0 0
T6 106565 17729 0 0
T7 235174 663 0 0
T8 296108 1552 0 0
T9 104227 36005 0 0
T10 453150 4413 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3110798 3013555 0 0
T1 24924 24786 0 0
T2 95 17 0 0
T3 2438 2379 0 0
T4 60197 60067 0 0
T5 103 17 0 0
T6 22200 21213 0 0
T7 959 871 0 0
T8 84601 84108 0 0
T9 2125 2034 0 0
T10 37761 36642 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 3287 0 0
T1 623121 49 0 0
T2 8749 1 0 0
T3 817152 1 0 0
T4 752480 51 0 0
T5 23647 1 0 0
T6 106565 11 0 0
T7 235174 1 0 0
T8 296108 15 0 0
T9 104227 24 0 0
T10 453150 11 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 645546591 0 0
T1 623121 621466 0 0
T2 8749 8682 0 0
T3 817152 817070 0 0
T4 752480 751712 0 0
T5 23647 23578 0 0
T6 106565 106556 0 0
T7 235174 235084 0 0
T8 296108 296054 0 0
T9 104227 103141 0 0
T10 453150 453050 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 646182817 2606556 0 0
DstReqKnown_A 3110798 3013555 0 0
SrcAckBusyChk_A 646182817 3284 0 0
SrcBusyKnown_A 646182817 645546591 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 2606556 0 0
T1 623121 39387 0 0
T2 8749 347 0 0
T3 817152 1327 0 0
T4 752480 19463 0 0
T5 23647 826 0 0
T6 106565 18145 0 0
T7 235174 644 0 0
T8 296108 1465 0 0
T9 104227 35930 0 0
T10 453150 4391 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3110798 3013555 0 0
T1 24924 24786 0 0
T2 95 17 0 0
T3 2438 2379 0 0
T4 60197 60067 0 0
T5 103 17 0 0
T6 22200 21213 0 0
T7 959 871 0 0
T8 84601 84108 0 0
T9 2125 2034 0 0
T10 37761 36642 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 3284 0 0
T1 623121 49 0 0
T2 8749 1 0 0
T3 817152 1 0 0
T4 752480 51 0 0
T5 23647 1 0 0
T6 106565 11 0 0
T7 235174 1 0 0
T8 296108 15 0 0
T9 104227 24 0 0
T10 453150 11 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 645546591 0 0
T1 623121 621466 0 0
T2 8749 8682 0 0
T3 817152 817070 0 0
T4 752480 751712 0 0
T5 23647 23578 0 0
T6 106565 106556 0 0
T7 235174 235084 0 0
T8 296108 296054 0 0
T9 104227 103141 0 0
T10 453150 453050 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
TotalCoveredPercent
Conditions141392.86
Logical141392.86
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_count_lo_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 646182817 5768957 0 0
DstReqKnown_A 3110798 3013555 0 0
SrcAckBusyChk_A 646182817 6320 0 0
SrcBusyKnown_A 646182817 645546591 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 5768957 0 0
T1 623121 101386 0 0
T2 8749 890 0 0
T3 817152 2670 0 0
T4 752480 50090 0 0
T5 23647 1747 0 0
T6 106565 50478 0 0
T7 235174 1645 0 0
T8 296108 4006 0 0
T9 104227 96626 0 0
T10 453150 11256 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3110798 3013555 0 0
T1 24924 24786 0 0
T2 95 17 0 0
T3 2438 2379 0 0
T4 60197 60067 0 0
T5 103 17 0 0
T6 22200 21213 0 0
T7 959 871 0 0
T8 84601 84108 0 0
T9 2125 2034 0 0
T10 37761 36642 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 6320 0 0
T1 623121 108 0 0
T2 8749 2 0 0
T3 817152 2 0 0
T4 752480 112 0 0
T5 23647 2 0 0
T6 106565 24 0 0
T7 235174 2 0 0
T8 296108 33 0 0
T9 104227 51 0 0
T10 453150 24 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 645546591 0 0
T1 623121 621466 0 0
T2 8749 8682 0 0
T3 817152 817070 0 0
T4 752480 751712 0 0
T5 23647 23578 0 0
T6 106565 106556 0 0
T7 235174 235084 0 0
T8 296108 296054 0 0
T9 104227 103141 0 0
T10 453150 453050 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
TotalCoveredPercent
Conditions141392.86
Logical141392.86
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T4,T5
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wdog_count_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 646182817 5505337 0 0
DstReqKnown_A 3110798 3013555 0 0
SrcAckBusyChk_A 646182817 6367 0 0
SrcBusyKnown_A 646182817 645546591 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 5505337 0 0
T1 623121 97285 0 0
T2 8749 882 0 0
T3 817152 2662 0 0
T4 752480 47171 0 0
T5 23647 1711 0 0
T6 106565 46781 0 0
T7 235174 1597 0 0
T8 296108 3723 0 0
T9 104227 87965 0 0
T10 453150 10316 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3110798 3013555 0 0
T1 24924 24786 0 0
T2 95 17 0 0
T3 2438 2379 0 0
T4 60197 60067 0 0
T5 103 17 0 0
T6 22200 21213 0 0
T7 959 871 0 0
T8 84601 84108 0 0
T9 2125 2034 0 0
T10 37761 36642 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 6367 0 0
T1 623121 108 0 0
T2 8749 2 0 0
T3 817152 2 0 0
T4 752480 112 0 0
T5 23647 2 0 0
T6 106565 25 0 0
T7 235174 2 0 0
T8 296108 33 0 0
T9 104227 51 0 0
T10 453150 24 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 645546591 0 0
T1 623121 621466 0 0
T2 8749 8682 0 0
T3 817152 817070 0 0
T4 752480 751712 0 0
T5 23647 23578 0 0
T6 106565 106556 0 0
T7 235174 235084 0 0
T8 296108 296054 0 0
T9 104227 103141 0 0
T10 453150 453050 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
TotalCoveredPercent
Conditions161593.75
Logical161593.75
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT28,T30,T32

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T6
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_cause_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 646182817 2536434 0 0
DstReqKnown_A 3110798 3013555 0 0
SrcAckBusyChk_A 646182817 2896 0 0
SrcBusyKnown_A 646182817 645546591 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 2536434 0 0
T1 623121 37828 0 0
T2 8749 354 0 0
T3 817152 1335 0 0
T4 752480 19045 0 0
T5 23647 878 0 0
T6 106565 19923 0 0
T7 235174 700 0 0
T8 296108 1680 0 0
T9 104227 35123 0 0
T10 453150 4859 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3110798 3013555 0 0
T1 24924 24786 0 0
T2 95 17 0 0
T3 2438 2379 0 0
T4 60197 60067 0 0
T5 103 17 0 0
T6 22200 21213 0 0
T7 959 871 0 0
T8 84601 84108 0 0
T9 2125 2034 0 0
T10 37761 36642 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 2896 0 0
T1 623121 42 0 0
T2 8749 1 0 0
T3 817152 1 0 0
T4 752480 44 0 0
T5 23647 1 0 0
T6 106565 11 0 0
T7 235174 1 0 0
T8 296108 15 0 0
T9 104227 20 0 0
T10 453150 11 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 646182817 645546591 0 0
T1 623121 621466 0 0
T2 8749 8682 0 0
T3 817152 817070 0 0
T4 752480 751712 0 0
T5 23647 23578 0 0
T6 106565 106556 0 0
T7 235174 235084 0 0
T8 296108 296054 0 0
T9 104227 103141 0 0
T10 453150 453050 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%