Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	873205720	5583951	0	0
wdog_bark_thold_rd_A	873205720	132775	0	0
wdog_bite_thold_rd_A	873205720	116053	0	0
wdog_ctrl_rd_A	873205720	115581	0	0
wdog_regwen_rd_A	873205720	133600	0	0
wkup_ctrl_rd_A	873205720	116084	0	0
wkup_thold_hi_rd_A	873205720	133161	0	0
wkup_thold_lo_rd_A	873205720	116183	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873205720	5583951	0	0
T1	844656	224178	0	0
T2	202529	72389	0	0
T3	8831	0	0	0
T4	124760	0	0	0
T5	327370	88969	0	0
T6	433661	165364	0	0
T7	607137	161976	0	0
T8	132376	0	0	0
T9	247796	0	0	0
T10	967798	0	0	0
T29	0	136583	0	0
T40	0	102353	0	0
T41	0	293452	0	0
T42	0	58950	0	0
T43	0	161730	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873205720	132775	0	0
T40	471209	10452	0	0
T41	137312	29281	0	0
T42	0	3413	0	0
T47	12274	0	0	0
T79	0	20894	0	0
T83	0	1967	0	0
T84	0	6844	0	0
T85	0	9994	0	0
T86	0	4883	0	0
T87	0	4733	0	0
T88	0	5513	0	0
T89	4308	0	0	0
T90	267176	0	0	0
T91	80571	0	0	0
T92	11670	0	0	0
T93	388437	0	0	0
T94	502296	0	0	0
T95	39428	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873205720	116053	0	0
T40	471209	9530	0	0
T41	137312	25197	0	0
T42	0	3026	0	0
T47	12274	0	0	0
T79	0	17507	0	0
T83	0	1860	0	0
T84	0	5623	0	0
T85	0	8857	0	0
T86	0	4168	0	0
T87	0	4194	0	0
T88	0	4711	0	0
T89	4308	0	0	0
T90	267176	0	0	0
T91	80571	0	0	0
T92	11670	0	0	0
T93	388437	0	0	0
T94	502296	0	0	0
T95	39428	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873205720	115581	0	0
T40	471209	9888	0	0
T41	137312	24983	0	0
T42	0	2802	0	0
T47	12274	0	0	0
T79	0	17741	0	0
T83	0	1761	0	0
T84	0	6031	0	0
T85	0	8943	0	0
T86	0	4300	0	0
T87	0	4511	0	0
T88	0	4796	0	0
T89	4308	0	0	0
T90	267176	0	0	0
T91	80571	0	0	0
T92	11670	0	0	0
T93	388437	0	0	0
T94	502296	0	0	0
T95	39428	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873205720	133600	0	0
T40	471209	10710	0	0
T41	137312	29314	0	0
T42	0	3513	0	0
T47	12274	0	0	0
T79	0	20495	0	0
T83	0	1862	0	0
T84	0	7011	0	0
T85	0	10820	0	0
T86	0	4879	0	0
T87	0	4723	0	0
T88	0	5379	0	0
T89	4308	0	0	0
T90	267176	0	0	0
T91	80571	0	0	0
T92	11670	0	0	0
T93	388437	0	0	0
T94	502296	0	0	0
T95	39428	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873205720	116084	0	0
T40	471209	9597	0	0
T41	137312	25904	0	0
T42	0	2843	0	0
T47	12274	0	0	0
T79	0	17804	0	0
T83	0	1922	0	0
T84	0	6022	0	0
T85	0	8440	0	0
T86	0	4419	0	0
T87	0	4371	0	0
T88	0	4944	0	0
T89	4308	0	0	0
T90	267176	0	0	0
T91	80571	0	0	0
T92	11670	0	0	0
T93	388437	0	0	0
T94	502296	0	0	0
T95	39428	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873205720	133161	0	0
T40	471209	10946	0	0
T41	137312	29612	0	0
T42	0	3234	0	0
T47	12274	0	0	0
T79	0	20001	0	0
T83	0	1921	0	0
T84	0	6958	0	0
T85	0	10919	0	0
T86	0	4949	0	0
T87	0	4941	0	0
T88	0	5393	0	0
T89	4308	0	0	0
T90	267176	0	0	0
T91	80571	0	0	0
T92	11670	0	0	0
T93	388437	0	0	0
T94	502296	0	0	0
T95	39428	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873205720	116183	0	0
T40	471209	9541	0	0
T41	137312	26105	0	0
T42	0	2690	0	0
T47	12274	0	0	0
T79	0	17796	0	0
T83	0	1614	0	0
T84	0	5620	0	0
T85	0	8942	0	0
T86	0	4303	0	0
T87	0	4135	0	0
T88	0	4811	0	0
T89	4308	0	0	0
T90	267176	0	0	0
T91	80571	0	0	0
T92	11670	0	0	0
T93	388437	0	0	0
T94	502296	0	0	0
T95	39428	0	0	0