Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	330209	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4059602	1		T1	17		T2	123376		T3	74634

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1079273	1		T1	1		T2	32778		T3	19768
values[0x0]	1552725	1		T1	15		T2	46958		T3	28408
values[0x1]	1757813	1		T1	6		T2	53670		T3	32048

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	148135	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4241676	1		T1	17		T2	129082		T3	77848

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16802	1		T2	521		T3	35		T9	171
valid_sources[0x01]	16912	1		T2	510		T3	537		T9	202
valid_sources[0x02]	18336	1		T2	520		T3	302		T5	2
valid_sources[0x03]	16535	1		T2	486		T3	314		T9	190
valid_sources[0x04]	16952	1		T2	518		T3	143		T9	191
valid_sources[0x05]	16984	1		T2	529		T3	230		T9	177
valid_sources[0x06]	15947	1		T2	540		T3	458		T9	201
valid_sources[0x07]	17038	1		T2	547		T3	95		T9	199
valid_sources[0x08]	17052	1		T2	546		T3	42		T9	183
valid_sources[0x09]	18685	1		T2	553		T3	466		T9	170
valid_sources[0x0a]	16659	1		T2	545		T3	164		T6	1
valid_sources[0x0b]	18481	1		T2	567		T3	279		T9	208
valid_sources[0x0c]	16984	1		T2	541		T3	101		T9	180
valid_sources[0x0d]	16938	1		T2	528		T3	34		T9	192
valid_sources[0x0e]	15810	1		T2	488		T3	30		T9	175
valid_sources[0x0f]	16134	1		T2	507		T3	274		T9	164
valid_sources[0x10]	17304	1		T2	524		T3	282		T9	204
valid_sources[0x11]	16203	1		T2	503		T3	286		T9	223
valid_sources[0x12]	17150	1		T2	502		T3	14		T9	202
valid_sources[0x13]	17426	1		T2	545		T3	565		T9	217
valid_sources[0x14]	17426	1		T2	497		T3	238		T9	206
valid_sources[0x15]	17218	1		T2	508		T3	457		T9	168
valid_sources[0x16]	18217	1		T2	489		T3	249		T9	168
valid_sources[0x17]	17779	1		T2	508		T3	397		T9	223
valid_sources[0x18]	17748	1		T2	529		T3	819		T9	206
valid_sources[0x19]	16416	1		T2	494		T3	272		T9	198
valid_sources[0x1a]	17557	1		T2	558		T3	522		T9	230
valid_sources[0x1b]	16910	1		T2	524		T3	68		T9	184
valid_sources[0x1c]	18337	1		T2	497		T3	593		T6	2
valid_sources[0x1d]	17230	1		T2	568		T3	376		T9	161
valid_sources[0x1e]	17272	1		T2	495		T3	183		T9	192
valid_sources[0x1f]	15967	1		T2	534		T3	195		T9	201
valid_sources[0x20]	15641	1		T2	544		T3	499		T9	185
valid_sources[0x21]	17445	1		T2	517		T3	324		T5	1
valid_sources[0x22]	16024	1		T2	529		T3	206		T9	189
valid_sources[0x23]	18135	1		T2	517		T3	279		T7	1
valid_sources[0x24]	16326	1		T2	542		T3	15		T9	211
valid_sources[0x25]	16757	1		T2	509		T3	75		T9	222
valid_sources[0x26]	16904	1		T2	538		T3	336		T9	192
valid_sources[0x27]	16756	1		T2	549		T3	314		T9	208
valid_sources[0x28]	15714	1		T2	530		T3	16		T9	170
valid_sources[0x29]	17295	1		T2	555		T3	85		T9	161
valid_sources[0x2a]	18161	1		T2	533		T3	303		T9	176
valid_sources[0x2b]	16372	1		T2	509		T3	115		T9	232
valid_sources[0x2c]	16487	1		T2	454		T3	48		T9	197
valid_sources[0x2d]	17255	1		T2	537		T3	112		T9	180
valid_sources[0x2e]	17155	1		T2	481		T3	624		T9	160
valid_sources[0x2f]	17087	1		T2	472		T3	300		T9	198
valid_sources[0x30]	15934	1		T2	532		T3	255		T9	198
valid_sources[0x31]	18769	1		T2	541		T3	223		T9	161
valid_sources[0x32]	17249	1		T2	518		T3	524		T9	193
valid_sources[0x33]	17554	1		T2	504		T3	373		T9	174
valid_sources[0x34]	17489	1		T2	495		T3	508		T5	2
valid_sources[0x35]	17554	1		T2	535		T3	85		T9	193
valid_sources[0x36]	15933	1		T2	511		T3	217		T9	207
valid_sources[0x37]	16980	1		T2	526		T3	284		T9	178
valid_sources[0x38]	17548	1		T2	510		T3	432		T9	197
valid_sources[0x39]	17482	1		T2	535		T3	130		T5	7
valid_sources[0x3a]	17766	1		T2	532		T3	22		T9	206
valid_sources[0x3b]	17670	1		T2	479		T3	471		T9	200
valid_sources[0x3c]	15917	1		T2	514		T3	152		T9	182
valid_sources[0x3d]	17374	1		T2	513		T3	170		T9	196
valid_sources[0x3e]	19571	1		T2	534		T3	334		T9	168
valid_sources[0x3f]	15801	1		T2	521		T3	470		T9	208
valid_sources[0x40]	16618	1		T2	499		T3	26		T9	185
valid_sources[0x41]	17733	1		T2	487		T3	619		T9	210
valid_sources[0x42]	16361	1		T2	493		T3	194		T9	180
valid_sources[0x43]	15858	1		T2	466		T3	24		T9	212
valid_sources[0x44]	18989	1		T2	529		T3	243		T9	166
valid_sources[0x45]	16566	1		T2	551		T3	346		T9	217
valid_sources[0x46]	17644	1		T2	495		T3	45		T9	163
valid_sources[0x47]	16601	1		T2	548		T3	491		T9	211
valid_sources[0x48]	17468	1		T2	558		T3	346		T9	211
valid_sources[0x49]	15385	1		T2	463		T3	397		T5	4
valid_sources[0x4a]	16415	1		T2	523		T3	81		T9	192
valid_sources[0x4b]	18352	1		T2	529		T3	139		T9	179
valid_sources[0x4c]	16971	1		T2	513		T3	370		T9	175
valid_sources[0x4d]	18055	1		T2	543		T3	149		T9	203
valid_sources[0x4e]	18047	1		T2	525		T3	669		T9	186
valid_sources[0x4f]	17941	1		T2	485		T3	135		T9	233
valid_sources[0x50]	16259	1		T2	499		T3	47		T9	189
valid_sources[0x51]	17385	1		T2	537		T3	589		T9	209
valid_sources[0x52]	16083	1		T2	522		T3	178		T9	175
valid_sources[0x53]	16380	1		T2	522		T3	459		T9	212
valid_sources[0x54]	16966	1		T2	569		T3	301		T9	214
valid_sources[0x55]	17060	1		T2	538		T3	546		T9	188
valid_sources[0x56]	17684	1		T2	498		T3	334		T9	142
valid_sources[0x57]	18054	1		T2	513		T3	340		T9	183
valid_sources[0x58]	16582	1		T2	572		T3	181		T9	177
valid_sources[0x59]	16638	1		T2	501		T3	173		T9	185
valid_sources[0x5a]	17838	1		T2	488		T3	351		T8	19
valid_sources[0x5b]	17887	1		T2	553		T3	69		T9	224
valid_sources[0x5c]	19797	1		T2	434		T3	811		T9	188
valid_sources[0x5d]	18292	1		T2	516		T3	435		T9	177
valid_sources[0x5e]	16058	1		T2	501		T3	29		T7	11
valid_sources[0x5f]	16745	1		T2	542		T3	517		T9	219
valid_sources[0x60]	16419	1		T2	515		T3	408		T9	170
valid_sources[0x61]	15483	1		T2	510		T3	271		T9	188
valid_sources[0x62]	15746	1		T2	535		T3	234		T9	179
valid_sources[0x63]	17949	1		T2	528		T3	660		T5	1
valid_sources[0x64]	17293	1		T2	533		T3	108		T9	198
valid_sources[0x65]	16395	1		T2	535		T3	170		T5	1
valid_sources[0x66]	17698	1		T2	556		T3	73		T9	198
valid_sources[0x67]	17469	1		T2	485		T3	557		T9	219
valid_sources[0x68]	17119	1		T2	501		T3	240		T9	201
valid_sources[0x69]	17511	1		T2	493		T3	289		T6	7
valid_sources[0x6a]	15550	1		T2	520		T3	459		T9	224
valid_sources[0x6b]	17064	1		T2	559		T3	156		T9	200
valid_sources[0x6c]	15486	1		T2	538		T3	101		T9	179
valid_sources[0x6d]	16672	1		T2	499		T3	259		T9	181
valid_sources[0x6e]	18418	1		T2	502		T3	359		T9	177
valid_sources[0x6f]	18004	1		T2	529		T3	362		T9	177
valid_sources[0x70]	18507	1		T2	524		T3	174		T4	22
valid_sources[0x71]	16624	1		T2	535		T3	734		T9	201
valid_sources[0x72]	18263	1		T2	505		T3	465		T9	176
valid_sources[0x73]	16450	1		T2	515		T3	102		T9	197
valid_sources[0x74]	17672	1		T2	529		T3	164		T9	199
valid_sources[0x75]	18565	1		T2	563		T3	263		T9	196
valid_sources[0x76]	17155	1		T2	512		T3	643		T9	217
valid_sources[0x77]	18266	1		T2	503		T3	425		T9	199
valid_sources[0x78]	18304	1		T2	499		T3	306		T9	221
valid_sources[0x79]	19213	1		T2	482		T3	29		T9	189
valid_sources[0x7a]	17969	1		T2	512		T3	794		T9	177
valid_sources[0x7b]	16472	1		T2	490		T3	797		T9	194
valid_sources[0x7c]	17454	1		T2	537		T3	185		T9	185
valid_sources[0x7d]	17630	1		T2	585		T3	540		T9	156
valid_sources[0x7e]	16415	1		T2	541		T3	12		T9	193
valid_sources[0x7f]	16497	1		T2	496		T3	458		T9	223
valid_sources[0x80]	18094	1		T2	552		T3	523		T9	187

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1012575

1

T1

1

T2

30822

T3

18692

values[0x0]

all_enables

biggest_size

1524423

1

T1

11

T2

46168

T3

27970

values[0x1]

all_enables

biggest_size

1522604

1

T1

5

T2

46386

T3

27972