Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	630515298	4796794	0	0
wdog_bark_thold_rd_A	630515298	98710	0	0
wdog_bite_thold_rd_A	630515298	85988	0	0
wdog_ctrl_rd_A	630515298	84973	0	0
wdog_regwen_rd_A	630515298	97532	0	0
wkup_ctrl_rd_A	630515298	84725	0	0
wkup_thold_hi_rd_A	630515298	97828	0	0
wkup_thold_lo_rd_A	630515298	86318	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630515298	4796794	0	0
T2	582611	149775	0	0
T3	236023	84009	0	0
T4	44753	0	0	0
T5	23413	0	0	0
T6	3519	0	0	0
T7	110157	0	0	0
T8	53759	0	0	0
T9	194560	51510	0	0
T10	171580	0	0	0
T11	9404	0	0	0
T39	0	132347	0	0
T40	0	80772	0	0
T41	0	26105	0	0
T42	0	103762	0	0
T43	0	25017	0	0
T44	0	27768	0	0
T45	0	218490	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630515298	98710	0	0
T32	0	17972	0	0
T43	135671	2543	0	0
T44	128019	2754	0	0
T45	578146	0	0	0
T47	0	5924	0	0
T75	0	4952	0	0
T76	0	2188	0	0
T77	0	4425	0	0
T78	0	15287	0	0
T79	0	6842	0	0
T80	0	12779	0	0
T81	8426	0	0	0
T82	49362	0	0	0
T83	25707	0	0	0
T84	553259	0	0	0
T85	44397	0	0	0
T86	10789	0	0	0
T87	292461	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630515298	85988	0	0
T32	0	14906	0	0
T43	135671	2270	0	0
T44	128019	2125	0	0
T45	578146	0	0	0
T47	0	4873	0	0
T75	0	4606	0	0
T76	0	1947	0	0
T77	0	3540	0	0
T78	0	13915	0	0
T79	0	5950	0	0
T80	0	11283	0	0
T81	8426	0	0	0
T82	49362	0	0	0
T83	25707	0	0	0
T84	553259	0	0	0
T85	44397	0	0	0
T86	10789	0	0	0
T87	292461	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630515298	84973	0	0
T32	0	15251	0	0
T43	135671	2158	0	0
T44	128019	2180	0	0
T45	578146	0	0	0
T47	0	5054	0	0
T75	0	4520	0	0
T76	0	1748	0	0
T77	0	3555	0	0
T78	0	13209	0	0
T79	0	5730	0	0
T80	0	11638	0	0
T81	8426	0	0	0
T82	49362	0	0	0
T83	25707	0	0	0
T84	553259	0	0	0
T85	44397	0	0	0
T86	10789	0	0	0
T87	292461	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630515298	97532	0	0
T32	0	17674	0	0
T43	135671	2432	0	0
T44	128019	2439	0	0
T45	578146	0	0	0
T47	0	5438	0	0
T75	0	4999	0	0
T76	0	1846	0	0
T77	0	4069	0	0
T78	0	15497	0	0
T79	0	6753	0	0
T80	0	13597	0	0
T81	8426	0	0	0
T82	49362	0	0	0
T83	25707	0	0	0
T84	553259	0	0	0
T85	44397	0	0	0
T86	10789	0	0	0
T87	292461	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630515298	84725	0	0
T32	0	15882	0	0
T43	135671	1966	0	0
T44	128019	2069	0	0
T45	578146	0	0	0
T47	0	5055	0	0
T75	0	4494	0	0
T76	0	1674	0	0
T77	0	3724	0	0
T78	0	12787	0	0
T79	0	5913	0	0
T80	0	11366	0	0
T81	8426	0	0	0
T82	49362	0	0	0
T83	25707	0	0	0
T84	553259	0	0	0
T85	44397	0	0	0
T86	10789	0	0	0
T87	292461	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630515298	97828	0	0
T32	0	17493	0	0
T43	135671	2462	0	0
T44	128019	2494	0	0
T45	578146	0	0	0
T47	0	5671	0	0
T75	0	5130	0	0
T76	0	2080	0	0
T77	0	4130	0	0
T78	0	15298	0	0
T79	0	6846	0	0
T80	0	13228	0	0
T81	8426	0	0	0
T82	49362	0	0	0
T83	25707	0	0	0
T84	553259	0	0	0
T85	44397	0	0	0
T86	10789	0	0	0
T87	292461	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630515298	86318	0	0
T32	0	15779	0	0
T43	135671	2274	0	0
T44	128019	2076	0	0
T45	578146	0	0	0
T47	0	5254	0	0
T75	0	4488	0	0
T76	0	1763	0	0
T77	0	3860	0	0
T78	0	12813	0	0
T79	0	6137	0	0
T80	0	11472	0	0
T81	8426	0	0	0
T82	49362	0	0	0
T83	25707	0	0	0
T84	553259	0	0	0
T85	44397	0	0	0
T86	10789	0	0	0
T87	292461	0	0	0