Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	313190	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3783129	1		T1	65975		T2	166		T3	214215

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1007063	1		T1	17376		T2	42		T3	56594
values[0x0]	1446243	1		T1	25414		T2	111		T3	81387
values[0x1]	1643013	1		T1	28878		T2	110		T3	93105

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	139892	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	3956427	1		T1	69082		T2	185		T3	223833

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16145	1		T1	325		T3	1833		T5	5
valid_sources[0x01]	14897	1		T1	280		T3	784		T5	1
valid_sources[0x02]	16662	1		T1	309		T3	822		T5	3
valid_sources[0x03]	14397	1		T1	240		T3	407		T5	1
valid_sources[0x04]	15496	1		T1	242		T3	1280		T6	634
valid_sources[0x05]	15179	1		T1	217		T3	1076		T5	2
valid_sources[0x06]	16348	1		T1	310		T3	569		T6	586
valid_sources[0x07]	16401	1		T1	278		T3	1152		T6	595
valid_sources[0x08]	16253	1		T1	299		T3	1267		T5	2
valid_sources[0x09]	15037	1		T1	259		T3	865		T5	2
valid_sources[0x0a]	16847	1		T1	384		T3	950		T6	592
valid_sources[0x0b]	15575	1		T1	301		T3	1065		T5	1
valid_sources[0x0c]	15056	1		T1	208		T3	650		T5	1
valid_sources[0x0d]	16282	1		T1	297		T3	800		T5	1
valid_sources[0x0e]	15463	1		T1	277		T3	800		T4	1
valid_sources[0x0f]	15184	1		T1	274		T3	316		T5	1
valid_sources[0x10]	14632	1		T1	267		T3	844		T5	1
valid_sources[0x11]	16134	1		T1	325		T3	1143		T5	1
valid_sources[0x12]	15480	1		T1	323		T3	472		T5	1
valid_sources[0x13]	15495	1		T1	253		T3	1148		T5	4
valid_sources[0x14]	16638	1		T1	239		T3	1191		T5	4
valid_sources[0x15]	15682	1		T1	324		T3	1016		T5	1
valid_sources[0x16]	15195	1		T1	325		T3	644		T4	1
valid_sources[0x17]	16008	1		T1	286		T3	1183		T5	1
valid_sources[0x18]	14825	1		T1	243		T3	554		T5	3
valid_sources[0x19]	17965	1		T1	284		T3	945		T5	1
valid_sources[0x1a]	15375	1		T1	295		T3	470		T5	4
valid_sources[0x1b]	15449	1		T1	317		T3	156		T4	2
valid_sources[0x1c]	15153	1		T1	273		T3	864		T5	3
valid_sources[0x1d]	16590	1		T1	223		T3	689		T5	2
valid_sources[0x1e]	15366	1		T1	184		T3	1216		T5	2
valid_sources[0x1f]	16197	1		T1	298		T3	397		T5	3
valid_sources[0x20]	16631	1		T1	336		T3	508		T5	2
valid_sources[0x21]	15114	1		T1	300		T3	310		T5	2
valid_sources[0x22]	14618	1		T1	248		T3	310		T5	1
valid_sources[0x23]	16390	1		T1	293		T3	612		T6	623
valid_sources[0x24]	16298	1		T1	228		T3	1499		T5	1
valid_sources[0x25]	15578	1		T1	231		T3	775		T5	1
valid_sources[0x26]	17004	1		T1	276		T3	1043		T4	3
valid_sources[0x27]	16440	1		T1	207		T3	846		T5	1
valid_sources[0x28]	16026	1		T1	334		T3	968		T5	3
valid_sources[0x29]	15841	1		T1	402		T3	758		T5	1
valid_sources[0x2a]	16771	1		T1	254		T3	671		T6	618
valid_sources[0x2b]	15490	1		T1	335		T3	772		T5	1
valid_sources[0x2c]	15706	1		T1	258		T3	1201		T5	1
valid_sources[0x2d]	15224	1		T1	261		T3	960		T6	509
valid_sources[0x2e]	16169	1		T1	292		T3	430		T5	2
valid_sources[0x2f]	15708	1		T1	243		T3	1290		T5	1
valid_sources[0x30]	16152	1		T1	208		T3	971		T5	1
valid_sources[0x31]	16500	1		T1	338		T3	1083		T5	1
valid_sources[0x32]	15126	1		T1	295		T3	495		T5	3
valid_sources[0x33]	16001	1		T1	349		T3	583		T6	572
valid_sources[0x34]	16430	1		T1	330		T3	1002		T6	586
valid_sources[0x35]	15836	1		T1	280		T3	1022		T5	3
valid_sources[0x36]	16994	1		T1	400		T3	935		T6	518
valid_sources[0x37]	16527	1		T1	249		T3	1220		T4	1
valid_sources[0x38]	17001	1		T1	331		T3	965		T5	2
valid_sources[0x39]	15005	1		T1	308		T3	551		T5	1
valid_sources[0x3a]	16979	1		T1	244		T3	1322		T5	4
valid_sources[0x3b]	16869	1		T1	212		T3	1101		T5	2
valid_sources[0x3c]	16128	1		T1	349		T3	997		T6	564
valid_sources[0x3d]	16118	1		T1	290		T3	1033		T5	2
valid_sources[0x3e]	15449	1		T1	338		T3	419		T5	2
valid_sources[0x3f]	15550	1		T1	232		T3	536		T5	2
valid_sources[0x40]	16176	1		T1	241		T3	689		T5	2
valid_sources[0x41]	15635	1		T1	267		T3	1369		T6	554
valid_sources[0x42]	16031	1		T1	270		T3	858		T5	1
valid_sources[0x43]	15136	1		T1	283		T3	1065		T6	498
valid_sources[0x44]	15730	1		T1	193		T3	1125		T4	1
valid_sources[0x45]	15975	1		T1	276		T3	1517		T5	1
valid_sources[0x46]	17569	1		T1	265		T3	1204		T5	3
valid_sources[0x47]	16822	1		T1	234		T3	1344		T6	597
valid_sources[0x48]	16086	1		T1	315		T3	581		T6	542
valid_sources[0x49]	15965	1		T1	245		T3	1106		T6	502
valid_sources[0x4a]	15453	1		T1	363		T3	726		T5	2
valid_sources[0x4b]	15254	1		T1	263		T3	758		T5	1
valid_sources[0x4c]	15597	1		T1	212		T3	793		T5	1
valid_sources[0x4d]	14672	1		T1	323		T3	1111		T5	4
valid_sources[0x4e]	17443	1		T1	263		T3	1512		T5	2
valid_sources[0x4f]	16118	1		T1	315		T3	787		T5	1
valid_sources[0x50]	16647	1		T1	229		T3	1714		T5	2
valid_sources[0x51]	15288	1		T1	280		T3	1163		T5	4
valid_sources[0x52]	16489	1		T1	249		T3	562		T5	2
valid_sources[0x53]	16826	1		T1	257		T3	1650		T5	2
valid_sources[0x54]	16273	1		T1	365		T3	953		T5	3
valid_sources[0x55]	14383	1		T1	282		T3	565		T5	1
valid_sources[0x56]	14944	1		T1	245		T3	1025		T6	612
valid_sources[0x57]	16919	1		T1	244		T3	663		T5	1
valid_sources[0x58]	16020	1		T1	253		T3	976		T5	1
valid_sources[0x59]	16142	1		T1	332		T3	1148		T6	598
valid_sources[0x5a]	15449	1		T1	285		T3	726		T6	518
valid_sources[0x5b]	16736	1		T1	298		T3	845		T6	613
valid_sources[0x5c]	16188	1		T1	296		T3	805		T5	1
valid_sources[0x5d]	14538	1		T1	220		T3	259		T5	1
valid_sources[0x5e]	16083	1		T1	242		T3	787		T5	6
valid_sources[0x5f]	15139	1		T1	392		T3	915		T5	1
valid_sources[0x60]	16526	1		T1	300		T3	989		T5	4
valid_sources[0x61]	16154	1		T1	258		T3	1262		T5	1
valid_sources[0x62]	15853	1		T1	299		T3	560		T6	587
valid_sources[0x63]	15697	1		T1	299		T3	357		T6	556
valid_sources[0x64]	14422	1		T1	311		T3	568		T5	1
valid_sources[0x65]	15604	1		T1	252		T3	320		T5	1
valid_sources[0x66]	16716	1		T1	252		T3	1449		T5	1
valid_sources[0x67]	16518	1		T1	370		T3	1009		T5	1
valid_sources[0x68]	16546	1		T1	338		T3	1415		T4	2
valid_sources[0x69]	17308	1		T1	253		T3	638		T6	556
valid_sources[0x6a]	16337	1		T1	261		T3	1370		T5	1
valid_sources[0x6b]	15752	1		T1	224		T3	655		T6	545
valid_sources[0x6c]	16260	1		T1	338		T3	1511		T6	585
valid_sources[0x6d]	16084	1		T1	262		T3	651		T5	2
valid_sources[0x6e]	17338	1		T1	291		T3	717		T6	580
valid_sources[0x6f]	16070	1		T1	293		T3	1164		T5	1
valid_sources[0x70]	15611	1		T1	337		T3	548		T6	536
valid_sources[0x71]	15185	1		T1	221		T3	298		T4	1
valid_sources[0x72]	16246	1		T1	221		T3	1130		T6	530
valid_sources[0x73]	16405	1		T1	284		T3	1049		T5	1
valid_sources[0x74]	16281	1		T1	276		T3	1008		T5	3
valid_sources[0x75]	16525	1		T1	303		T3	1465		T6	544
valid_sources[0x76]	17608	1		T1	295		T3	1381		T6	557
valid_sources[0x77]	15307	1		T1	375		T3	512		T6	521
valid_sources[0x78]	18021	1		T1	283		T3	746		T5	3
valid_sources[0x79]	16383	1		T1	255		T3	1128		T5	1
valid_sources[0x7a]	17028	1		T1	291		T3	1294		T5	2
valid_sources[0x7b]	16093	1		T1	263		T3	751		T6	557
valid_sources[0x7c]	15797	1		T1	259		T3	746		T4	1
valid_sources[0x7d]	18004	1		T1	276		T3	825		T5	4
valid_sources[0x7e]	16396	1		T1	235		T3	901		T5	3
valid_sources[0x7f]	15949	1		T1	252		T3	467		T5	2
valid_sources[0x80]	15630	1		T1	268		T3	511		T5	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

943711

1

T1

16259

T2

24

T3

53455

values[0x0]

all_enables

biggest_size

1419658

1

T1

24919

T2

79

T3

80082

values[0x1]

all_enables

biggest_size

1419760

1

T1

24797

T2

63

T3

80678